Author Topic: GW Instek GDS-2000E teardown /short review, comparison with Rigol DS2000(A)  (Read 14472 times)

0 Members and 1 Guest are viewing this topic.

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv
Pin 10 and 11 in 6518 amplifier is SDIO and SCLK
Not any kind of differential analog output
Hmm, but they have aux output. though it's not apparent if is used.
 

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv
This is important difference.
Input MUX + 180 degree clock phase shift between internal 2 ADC.
What prevents you from doing the phase shift in ADC08DL502?
 

Offline rf-loop

  • Super Contributor
  • ***
  • Posts: 3561
  • Country: cn
  • Born with DLL21 in hand
On the 2 channel versions it remains 1 GSPS regardless how many channels are used.

Do they have two ADC08DL502 chip also in 2 channel models so that both channels can use separate ADC chip?

With one ADC08DL502 can not do 2 channel 1GSa/s.

How they do true 1GSa/s even for one channel with one ADC08DL502 is also big question.
If practice and theory is not equal it tells that used application of theory is wrong or the theory itself is wrong.
-
Harmony OS
 

Offline rf-loop

  • Super Contributor
  • ***
  • Posts: 3561
  • Country: cn
  • Born with DLL21 in hand
This is important difference.
Input MUX + 180 degree clock phase shift between internal 2 ADC.
What prevents you from doing the phase shift in ADC08DL502?

I have not seen this function in ADC08DL502  One common clock input to both ADC.
Inside ADC08D500 there is also one common clock to to both adc but inside chipe there is selectable 180 degree phase shift. In this DES operation mode also phase shift is internally calibrated.
Quote
The ADC08D500 also includes an automatic clock phase background calibration feature which can be used in
DES mode to automatically and continuously adjust the clock phase of the I and Q channel. This feature
removes the need to adjust the clock phase setting manually and provides optimal Dual-Edge Sampling ENOB
performance
ADC08DL502 do not have at all this DES mode (Internal interleave mode)


And then, how you do 1GSa/s  if you have selected CH1 and CH2 for use and both have 1GSa/s and how it is done if CH1 and CH3 is selected and then both have 1GSa/s.
(this is why ask 2 input from 4 possible combinations and your result was that what ever 2 is selected there is 1GSa/s for both selected cannels.)

I want only know how they do this. (I have not claimed they can not do)
« Last Edit: May 08, 2016, 09:52:42 am by rf-loop »
If practice and theory is not equal it tells that used application of theory is wrong or the theory itself is wrong.
-
Harmony OS
 

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv
I have not seen this function in ADC08DL502
You do have 2 independent ADCs in it. Shift the clocks with FPGA.
EDIT, I had a brainfuck, following is not true.
I've done some poking measurements. There is external muxing going on. Even more funny, When you have only ch 4 enabled, signal goes to the both inputs of the ADC on the right(on the picture I provided) which is located above the first 2 channels  :scared:
Even more funny, when you have CH1 and CH4 enabled. Signal from CH4 goes to the right ADC, CH1 to the left ADC  :-DD.
« Last Edit: May 08, 2016, 10:51:53 am by wraper »
 

Offline rf-loop

  • Super Contributor
  • ***
  • Posts: 3561
  • Country: cn
  • Born with DLL21 in hand
I have not seen this function in ADC08DL502
You do have 2 independent ADCs in it. Shift the clocks with FPGA.
I've done some poking measurements. There is external muxing going on. Even more funny, When you have only ch 4 enabled, signal goes to the both inputs of the ADC on the right(on the picture I provided) which is located above the first 2 channels  :scared:
Even more funny, when you have CH1 and CH4 enabled. Signal from CH4 goes to the right ADC, CH1 to the left ADC  :-DD.

For clarify: Do you mean 2 independend ADC chips (what both include 2 ADC,)

Interesting case...very interesting.

If Signal from example CH1 (alone in use)  go to to two separate ADC chip, then there can phase shift but it leads many problems what need solve related to clock timing accuracy (jitter/phase noise/phase accuracy). Then also lot of do with different analog side signal pathways skev. Also amplitudes need really match. And in this case there is not inter chip automatic calibrations for help matching two interleaved ADC's in separate chips)
« Last Edit: May 08, 2016, 10:11:36 am by rf-loop »
If practice and theory is not equal it tells that used application of theory is wrong or the theory itself is wrong.
-
Harmony OS
 

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv
Hmm, probably I had some brainfuck, measuring this again. EDIT, it certainly was.
« Last Edit: May 08, 2016, 10:31:35 am by wraper »
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 21126
  • Country: nl
    • NCT Developments
If Signal from example CH1 (alone in use)  go to to two separate ADC chip, then there can phase shift but it leads many problems what need solve related to clock timing accuracy (jitter/phase noise/phase accuracy). Then also lot of do with different analog side signal pathways skev. Also amplitudes need really match. And in this case there is not inter chip automatic calibrations for help matching two interleaved ADC's in separate chips)
As far as I can see the VGAs (LMH6518) drive each ADC so it is possible to compensate for amplitude differences before each signal goes into the ADC. For this purpose the GDS2000E has a special calibrator output which is used during the self calibration/adjustment procedure. The frequencies are too low to have serious problems with skew (A 1ns delay needs about 30cm of trace length).  I think they use the transistors/diodes in the circuit to do the signal routing. The 8 pin SOIC is an AD8510 JFET amplifier to amplify/buffer the signal from the input attenuator. From there the signal goes into various transistors/diodes which seem to have no appearant other function. In a more classical oscilloscope design the output from the JFET amplifier would go straight into the VGA but it doesn't. So by logic deduction the multiplexing must happen by the extra transistors/diodes. It could be a simple JFET switch approach:


edit: The 2SK508 JFET has package marking K52 (one of the transistors visible in the photos) so that is a pretty solid support for the discrete multiplexer theory.
« Last Edit: May 08, 2016, 11:21:26 am by nctnico »
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv
After measuring back and forth, in the end there appears no analog switching going on. Channels are directly fed into the ADCs. Some fishy wizardry is going on. Maybe they are overclocking ADCs? BTW changing sample rate or switching off the channels does not seem to affect ADC temperature on the thermal imager. One ADC is about 50oC, Another 54oC That with cover removed of course.
 

Offline rf-loop

  • Super Contributor
  • ***
  • Posts: 3561
  • Country: cn
  • Born with DLL21 in hand
The frequencies are too low to have serious problems with skew (A 1ns delay needs about 30cm of trace length).

Ok, perhaps it is solved or guessed  what they perhaps do. (when I have been writing @wraper  last message make this my comment too optimistic)

IF they do "Ping-Pong" interleaving with two separate ADC.
Do you think 1ns delay there on the board in practice is 30cm... perhaps I'm also Santa Claus.
Time skew between two pingpong interleaved ADC is - how I say it nicely - still critical.

1ns is long time! It is whole 360 degree in 1GSa/s system.


Take very extremely simplified thinking, so that all can think it just calculating in head without more math. Lets think there 1GSa/s samplerate done with two 500MSa/s PingPong interleaved ADC and system itself is ideal and after one input signal goes ideally to both of these clocked ideally and ADC's linearity and amplitude etc all is ideally matched and they have ideal 180 degree phase shift.

Now, 200MHz scope rough risetime is 2ns. For simplify lets think there is 256 FS but this input signal make linear 200 ADC step change  in 2ns. So, 100step in 1ns.  In 100ps it change 10 step etc... this time error is directly translated to ADC sample point level error.

Do you still think time skev do not mean. If there is some kind of calibration for this, how it adjust these picoseconds. Programmable delay line?    Static delay is simple case. But also clocking separate ADC chips without any meaningful jitter is bit challenging when it need do cheap.
« Last Edit: May 08, 2016, 12:14:45 pm by rf-loop »
If practice and theory is not equal it tells that used application of theory is wrong or the theory itself is wrong.
-
Harmony OS
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 21126
  • Country: nl
    • NCT Developments
Do you still think time skev do not mean. If there is some kind of calibration for this, how it adjust these picoseconds. Programmable delay line?    Static delay is simple case. But also clocking separate ADC chips without any meaningful jitter is bit challenging when it need do cheap.
The ADC08DL502 ADCs have a clock phase adjust control in 0.2ps steps.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline siggi

  • Regular Contributor
  • *
  • Posts: 195
  • Country: ca
After measuring back and forth, in the end there appears no analog switching going on. Channels are directly fed into the ADCs. Some fishy wizardry is going on. Maybe they are overclocking ADCs? BTW changing sample rate or switching off the channels does not seem to affect ADC temperature on the thermal imager. One ADC is about 50oC, Another 54oC That with cover removed of course.
From the data sheet it looks like there are ADC registers that allow skewing the sample clock. The range mentioned is 2.1ns - would that be sufficient?
If you have a logic analyzer handy, maybe you could sniff the serial input to the ADCs?
 

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv
After measuring back and forth, in the end there appears no analog switching going on. Channels are directly fed into the ADCs. Some fishy wizardry is going on. Maybe they are overclocking ADCs? BTW changing sample rate or switching off the channels does not seem to affect ADC temperature on the thermal imager. One ADC is about 50oC, Another 54oC That with cover removed of course.
From the data sheet it looks like there are ADC registers that allow skewing the sample clock. The range mentioned is 2.1ns - would that be sufficient?
If you have a logic analyzer handy, maybe you could sniff the serial input to the ADCs?
I already spent more time than I should on figuring out this. Also, I'll be in another city for the whole next week starting from tomorrow, and actually don't have much of free time because I need to finish one project.
Poking here and there too much vastly increase the chances to kill this scope too.
 

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv
Sampling rate doesn't drop unless 3 channels are enabled simultaneously. So considering signal measurements I made on ADC inputs, my best bet is overclocked ADCs.

CH1 enabled, 1 GSPS


CH 1 & 2 enabled, 1 GSPS


CH 1, 2, 3 enabled, 500 MSPS


Now, 200MHz scope rough risetime is 2ns. For simplify lets think there is 256 FS but this input signal make linear 200 ADC step change  in 2ns. So, 100step in 1ns.  In 100ps it change 10 step etc... this time error is directly translated to ADC sample point level error.

Do you still think time skev do not mean. If there is some kind of calibration for this, how it adjust these picoseconds. Programmable delay line?    Static delay is simple case. But also clocking separate ADC chips without any meaningful jitter is bit challenging when it need do cheap.
The fact is, Rigol and GW instek are interleaving multiple slow ADCs in their older models - GDS-1000A/A-U and DS1000E.
« Last Edit: May 08, 2016, 01:37:27 pm by wraper »
 

Offline fanOfeeDIY

  • Supporter
  • ****
  • Posts: 403
  • Country: jp
    • YouTube Channel

I have now readed several times Ti data sheets about 08D500, 08D502 and 08DL502

I have one question. How they have done this 1GSa/s.

http://www.ti.com/lit/ds/symlink/adc08d500.pdf     2x500MSa/s  or 1GSa/s interleaved.
This is only what have interleaved mode for 1GSa/s if read Ti data sheets about these ADC versions.

http://www.ti.com/lit/ds/symlink/adc08d502.pdf     2x500MSa/s

http://www.ti.com/lit/ds/symlink/adc08dl502.pdf    2x500MSa/s

This is purely my guest and just my imagination.

I have a feeling that they bought all three of the ADCs, 08D500, 08D502 and 08DL502 and, and, and :)
they tried the DES enable bit  on address Dh and found that the bit enables DES on even 08DL502.
It is possible if TI is using the same die, and selling them differently with yield inspection.
The one passed the DES will be sold as 08D500 and the one did not pass or did not check for reducing the cost of qa as 08DL502.
Then GW instek might buying many of 08DL502 and select by them self which DES works.

Normally this is difficult to be allowed when you work as the product manager in inflexible company, but the world could be flexible.
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 21126
  • Country: nl
    • NCT Developments
Sampling rate doesn't drop unless 3 channels are enabled simultaneously. So considering signal measurements I made on ADC inputs, my best bet is overclocked ADCs.
I agree. TI recommends using a copper area as a heatsink but GW Instek choose to put relatively large heatsinks on top of the ADCs.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Online wraper

  • Supporter
  • ****
  • Posts: 13195
  • Country: lv

I have now readed several times Ti data sheets about 08D500, 08D502 and 08DL502

I have one question. How they have done this 1GSa/s.

http://www.ti.com/lit/ds/symlink/adc08d500.pdf     2x500MSa/s  or 1GSa/s interleaved.
This is only what have interleaved mode for 1GSa/s if read Ti data sheets about these ADC versions.

http://www.ti.com/lit/ds/symlink/adc08d502.pdf     2x500MSa/s

http://www.ti.com/lit/ds/symlink/adc08dl502.pdf    2x500MSa/s

This is purely my guest and just my imagination.

I have a feeling that they bought all three of the ADCs, 08D500, 08D502 and 08DL502 and, and, and :)
they tried the DES enable bit  on address Dh and found that the bit enables DES on even 08DL502.
It is possible if TI is using the same die, and selling them differently with yield inspection.
The one passed the DES will be sold as 08D500 and the one did not pass or did not check for reducing the cost of qa as 08DL502.
Then GW instek might buying many of 08DL502 and select by them self which DES works.

Normally this is difficult to be allowed when you work as the product manager in inflexible company, but the world could be flexible.
I rather suspect that they found that dual 1 GSPS ADC from Ti uses the same die as this 2x 500 MSPS one.
They must be overclocking, otherwise I don't understand how do they get 1 GSPS on 2 channels simultaneously while using one ADC (CH 1&2 or CH 3&4 scenario).
 

Offline rf-loop

  • Super Contributor
  • ***
  • Posts: 3561
  • Country: cn
  • Born with DLL21 in hand
So or so. All is possible. But also it IS possible to do system where is total 4 channel.
Two ADC chip what both have two internal  500MSa/s ADC (without internal inteleaving feature and both internals have same clock)
And so that what ever 2 channel is in use it is 1GSa/s for both selected channel.
If then turn on what ever one channel more it drops to 500MSa/s for all channels in use.

This need external Mux and CH select analog switch system before ADC and when it is in 1GSa/s mode other ADC chip need clocked interleaved and because this is in principle two ADC pingpong inteleaving timing is quite simple. There is just two these systems.  But if it is like this then it need that also 2 channel model have still 2 these ADC.

Idea is that in two channel mode other chip get inverse clock (180 degree phase and this can do even with clock delay adjustment inside chip) and during cal procedure fine adjusted for enough low signal skev (related to clock).
If both chips have ADC A and B then A inputs connected together and B inputs connected together.
Then example one Ch input connected to this A  and what ever other Ch  input connected to this B.

If one Ch alone then just connected alone to ADC input link A or B.

If more than 2 channel then links A and B need open and both chips clock to same phase.

It works but why do this... (IF they have done something like this)

(If they have found that internally chips are same but not factory quaranteed... this is totally other and much much more easy (and cheap) case)
« Last Edit: May 08, 2016, 02:21:33 pm by rf-loop »
If practice and theory is not equal it tells that used application of theory is wrong or the theory itself is wrong.
-
Harmony OS
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf