Hacking the HDO1k/HDO4k Rigol 12 bit scope

[markone]

Rigol EU keep it's promise and delivered the HDO1072 scope today.

Same thing here with an HDO1074 purchased during Black Fiday sale.

Attached is the file rigol.go modified for HDO1000. (just two options from the whole list - BW7T20 and RLU).
For reverting to factory license configuration: :SYSTem:OPTion:UNINSTall.
Many thanks to AlphaRne and all that helped with this!

The scope is pretty impressive with this new UI, low noise frontend, and  sturdy aspect, and not the last web interface which is as fast as those from RTB2k series.

Same feeling here, web interface impressed me as well,  from initial experience I would say that this DSO is a real bargain

Cons: noisy fan.

I can confirm, I would add that during first couple of minutes FAN also exhibited some sort of rattling/buzzing sound, later disappeared.

The other con is that serial decoder is a bug fest, but i'm aware it's not the main feature for a 12bit scope.   

LE: @markone - is about the web interface (SCPI Panel Control)

I do know what it is and where it is but ... I do not know what to type in ... 

Have I missed any guide ?

[markone]

-snip
I do know what it is and where it is but ... I do not know what to type in ... 

Have I missed any guide ?

Sorry, understood now ... 

[lgo51]

Vendor experiences for scoring an HD1074, USA preferred but open to deals 

Cheers

[trinacria]

The other con is that serial decoder is a bug fest, but i'm aware it's not the main feature for a 12bit scope.

It's weird that on a 12 -bit scope with SMPS waveforms in the marketing material, they chose to include a serial decoder instead of power analysis.

[Fungus]

Rigol EU keep it's promise and delivered the HDO1072 scope today.

The scope is pretty impressive with this new UI, low noise frontend, and  sturdy aspect, and not the last web interface which is as fast as those from RTB2k series.
Cons: noisy fan.

Looks very nice.

[Fungus]

It's weird that on a 12 -bit scope with SMPS waveforms in the marketing material, they chose to include a serial decoder instead of power analysis.

Power analysis is in the HDO4000.

(and might be a hack-option in the HDO1000...)

[skander36]

It's weird that on a 12 -bit scope with SMPS waveforms in the marketing material, they chose to include a serial decoder instead of power analysis.

Power analysis is in the HDO4000.

(and might be a hack-option in the HDO1000...)

I have tried to activate it (PWR) on HDO1K but I did not receive any message.
The hardware is the same, but this is a software app so it can be "brought to life". Maybe for a future hack.

[aurel]

Rigol EU keep it's promise and delivered the HDO1072 scope today.

Same thing here with an HDO1074 purchased during Black Fiday sale.

Exactly the same here. HDO1074 purchased on Black Friday from rigolshop.eu, received yesterday.

Attached is the file rigol.go modified for HDO1000. (just two options from the whole list - BW7T20 and RLU).
For reverting to factory license configuration: :SYSTem:OPTion:UNINSTall.
Many thanks to AlphaRne and all that helped with this!

The scope is pretty impressive with this new UI, low noise frontend, and  sturdy aspect, and not the last web interface which is as fast as those from RTB2k series.

Same feeling here, web interface impressed me as well,  from initial experience I would say that this DSO is a real bargain

I totally share the feeling.

Now I need to say thanks a lot to AlphaRne !
License generation worked easily and flawlessly.
Just beware that you need to rename rgtool.txt to rgtool.go before trying to run it, else the go compiler will fail with an unhelpful error message.

[markone]

I do know zero about Android programming and probably I'm going to make a silly question : the application program that manages the scope is in binary compiled form or is a container of readable java scripts ? 

I ask this trying to understand if the huge amount of capture memory left unused also with 100M upgrade applied (provided that HDO1000 boards are still like the one analyzed by David) could be used, in the future, with a software hack.

I guess that most depends on hoe the FPGA is involved in the process.

[Martin72]

Why should this be unleft ?

[markone]

Why should this be unleft ?

Because HDO1000's board mounts same FPGA memory chips of HDO4000 board and the latter is upgradable to 500Ms (the first one "only" 100Ms).

[TK]

I do know zero about Android programming and probably I'm going to make a silly question : the application program that manages the scope is in binary compiled form or is a container of readable java scripts ? 

I ask this trying to understand if the huge amount of capture memory left unused also with 100M upgrade applied (provided that HDO1000 boards are still like the one analyzed by David) could be used, in the future, with a software hack.

I guess that most depends on hoe the FPGA is involved in the process.

Signal capture memory is different than RAM where you run the OS.

[Martin72]

@Markone:
In my amateur mind this memory would be filling until it´s full or auto memory got control on it.
Or you control it manually.
It´s not the RAM of the system where you have the situation that not all capacity will be used.

[markone]

I do know zero about Android programming and probably I'm going to make a silly question : the application program that manages the scope is in binary compiled form or is a container of readable java scripts ? 

I ask this trying to understand if the huge amount of capture memory left unused also with 100M upgrade applied (provided that HDO1000 boards are still like the one analyzed by David) could be used, in the future, with a software hack.

I guess that most depends on hoe the FPGA is involved in the process.

Signal capture memory is different than RAM where you run the OS.

I've never said otherwise, I'll try to explain better.

I assume that capture memory is the FPGA external memory, the famous 4 chips identical in both models, of course not SOC memory where the control APP runs.

FPGA manages directly capture memory, SOC manages FPGA, both are involved and if FPGA code must be changed for some reasons I guess the game would be much harder.

To recap :

HDO1000 FPGA memory size = HDO4000 FPGA memory size

HDO1000 100 Mpts max      != HDO4000 500 Mpts  max

It would be VERY nice to bring 500 Mpts to HDO1000.

Of course I understand that's not a trivial process, it should be an adaptation of HDO4000 Android APP to run on HDO1000 boards, hence my question about Android APP.

I hope this time is more understandable (useless to say, i'm not english mother tongue  ).

[tautech]

Try using Mpts and everyone will be on the same page.

[markone]

Try using Mpts and everyone will be on the same page.

Got it 

[skander36]

I do know zero about Android programming and probably I'm going to make a silly question : the application program that manages the scope is in binary compiled form or is a container of readable java scripts ? 

I ask this trying to understand if the huge amount of capture memory left unused also with 100M upgrade applied (provided that HDO1000 boards are still like the one analyzed by David) could be used, in the future, with a software hack.

I guess that most depends on hoe the FPGA is involved in the process.

They are binary. You can download the FW for HDO4K from Rigol site and unzip it to see them. As TV 84 say you can dump the memory(JTAG) to see some internals ...

[markone]

I do know zero about Android programming and probably I'm going to make a silly question : the application program that manages the scope is in binary compiled form or is a container of readable java scripts ? 

I ask this trying to understand if the huge amount of capture memory left unused also with 100M upgrade applied (provided that HDO1000 boards are still like the one analyzed by David) could be used, in the future, with a software hack.

I guess that most depends on hoe the FPGA is involved in the process.

They are binary. You can download the FW for HDO4K from Rigol site and unzip it to see them. As TV 84 say you can dump the memory(JTAG) to see some internals ...

It seems strange that they published FW updated for 4K and not 1K, being practically identical.

What is the tool to inspect the FW .GEL file ?

[skander36]

Just unzip.
Also the apk files.

[bob808]

The readme.txt file in the FPGA folder has this content:

Code: [Select]

FPGA bit文件说明

按照FPGA器件型号
 A100T 标识符
 A75T  标识符 B

按照ADC颗粒(采样率)
2ADC 4GSa/s 标识符 S4
1ADC 2GSa/s 标识符 S2


HDO4000-FPGA-A100T
bit1 SPU_H12S4_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S4.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S4_bode.bit         Bode功能版本，无高分辨率

HDO2000/1000-FPGA-A100T
bit1 SPU_H12S2_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S2.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S2_bode.bit         Bode功能版本，无高分辨率



HDO4000-FPGA-A75T
bit1 SPU_H12S4B_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S4B.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S4B_bode.bit         Bode功能版本，无高分辨率

HDO2000/1000-FPGA-A75T
bit1 SPU_H12S2B_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S2B.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S2B_bode.bit         Bode功能版本，无高分辨率 

There seem to be two FPGAs mentioned A100T and A75T. There seem to be files for both HDO4000 and HDO1000 with either FPGA option. 

edit:
I ran it through a translator:

Code: [Select]

FPGA bit file description

By FPGA device type
 A100T Identifier 
 A75T Identifier B
 
According to ADC particle (sampling rate)
2ADC 4GSa/s Identifier S4
1ADC 2GSa/s Identifier S2


HDO4000-FPGA-A100T
bit1 SPU_H12S4_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S4.bit Regular oscilloscope program, no Bode map function
bit3 SPU_H12S4_bode.bit Bode function version, no high resolution

HDO2000/1000-FPGA-A100T
bit1 SPU_H12S2_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S2.bit Regular oscilloscope program, no Bode map function
bit3 SPU_H12S2_bode.bit Bode function version, no high resolution



HDO4000-FPGA-A75T
bit1 SPU_H12S4B_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S4B.bit General oscilloscope program, no Bode map function
bit3 SPU_H12S4B_bode.bit Bode function version, no high resolution

HDO2000/1000-FPGA-A75T
bit1 SPU_H12S2B_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S2B.bit Regular oscilloscope program, no Bode map function
bit3 SPU_H12S2B_bode.bit Bode function version, no high resolution

[skander36]

There not seem to have much choices. For HDO1K with A100T, only S2 bit2 can be used, as S4 need two ADC's, bit1 is for testing and bit3 is maybe for a future version with AWG.
Also in the frontend is a little difference that can be a filter to limit the bandwith of the frontend amplifier to 2-300 MHz. Tho I wish I'm wrong ...

[bob808]

Yeah my best guess is that the frontend filters are different, at least in part values.
Interesting that Dave's photos for HDO1k/HDO4k shows that both have A100T, no A75T. The FPGA files also imply there would be a A75T on the HDO4k series as well.
On a hardware level it would be interesting to see the innards of HDO1072.

[markone]

There not seem to have much choices. For HDO1K with A100T, only S2 bit2 can be used, as S4 need two ADC's, bit1 is for testing and bit3 is maybe for a future version with AWG.
Also in the frontend is a little difference that can be a filter to limit the bandwith of the frontend amplifier to 2-300 MHz. Tho I wish I'm wrong ...

I would make sense,  300MHz BW @ 2GS/s are already at limit.

In my opinion, provided that HDO1K is still carrying same HDO4K FPGA memory chips, hacking max capture Mpts and enable 50ohm option would be still gorgeus.

[markone]

The readme.txt file in the FPGA folder has this content:

Code: [Select]

FPGA bit文件说明

按照FPGA器件型号
 A100T 标识符
 A75T  标识符 B

按照ADC颗粒(采样率)
2ADC 4GSa/s 标识符 S4
1ADC 2GSa/s 标识符 S2


HDO4000-FPGA-A100T
bit1 SPU_H12S4_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S4.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S4_bode.bit         Bode功能版本，无高分辨率

HDO2000/1000-FPGA-A100T
bit1 SPU_H12S2_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S2.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S2_bode.bit         Bode功能版本，无高分辨率



HDO4000-FPGA-A75T
bit1 SPU_H12S4B_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S4B.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S4B_bode.bit         Bode功能版本，无高分辨率

HDO2000/1000-FPGA-A75T
bit1 SPU_H12S2B_SelfTest.bit     完成芯片和板级自检；包括DDR校准参数回读。
bit2 SPU_H12S2B.bit              常规示波器程序，无Bode图功能
bit3 SPU_H12S2B_bode.bit         Bode功能版本，无高分辨率 

There seem to be two FPGAs mentioned A100T and A75T. There seem to be files for both HDO4000 and HDO1000 with either FPGA option. 

edit:
I ran it through a translator:

Code: [Select]

FPGA bit file description

By FPGA device type
 A100T Identifier 
 A75T Identifier B
 
According to ADC particle (sampling rate)
2ADC 4GSa/s Identifier S4
1ADC 2GSa/s Identifier S2


HDO4000-FPGA-A100T
bit1 SPU_H12S4_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S4.bit Regular oscilloscope program, no Bode map function
bit3 SPU_H12S4_bode.bit Bode function version, no high resolution

HDO2000/1000-FPGA-A100T
bit1 SPU_H12S2_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S2.bit Regular oscilloscope program, no Bode map function
bit3 SPU_H12S2_bode.bit Bode function version, no high resolution



HDO4000-FPGA-A75T
bit1 SPU_H12S4B_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S4B.bit General oscilloscope program, no Bode map function
bit3 SPU_H12S4B_bode.bit Bode function version, no high resolution

HDO2000/1000-FPGA-A75T
bit1 SPU_H12S2B_SelfTest.bit Complete chip and board level self-test; including DDR calibration parameter readback.
bit2 SPU_H12S2B.bit Regular oscilloscope program, no Bode map function
bit3 SPU_H12S2B_bode.bit Bode function version, no high resolution

So it seems that FPGA size is not the limiting factor, both HDO4K & HDO4K have to work with both P/N, this is a very good news.

[skander36]

Interesting that they have put all 9 FPGA versions in that folder. Wonder why ...
For 50 ohm, even that the switch can be "moved", that need to be compensated as a value, along the signal path.