PC: what do you think about the possibility of removing the FLASH for F1c100, and connecting the wires to the flash FPGA. There, I think it would be possible to write the code for the FPGA. Anyway, the new program in the FPGA will end the support of the FNIRSI software.
This might bring a conflict when starting up the system, where the F1C100s reads the FLASH and the two masters collide. Maybe not a problem when the F1C100s starts from the SD card, but I have no clear picture of what actually is done on startup of the F1C100s. The FPGA as is now will directly output a clock onto the FLASH chip and read data from it to load into the FPGA configuration memory. So make sure the F1C100s does not interfere with this until the FPGA is done.
A better option might be to change the startup mode of the FPGA to serial slave, and have the F1C100s load it with data from the SD card. This way there is no need to write any FLASH memory, and both of the FLASH chips can be removed. This does need investigation into how the data has to be presented to the FPGA.
It is a big hardware change either way, and how many are willing and able to do this?