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| Hacking the Siglent SDM3055 Bench DMM |
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| Kleinstein:
Not having an extra AZ mode can happen with the SD ADC chips. The ADC chips internally often do some kind of chopping and have very little drift. If combined with a chopper stabilized input amplifier, there may very well be no real need for an AZ mode. Given a 50 samples per second reading rate the RMS noise is not so bad. The question is more the large span. So the noise seems to be not just white noise, but somewhat different, e.g. with some outliers. I may be worth looking at the noise in the time domain or look at the Allan varaiance. Resudual mains hum would cause a relatively small span compared to the RMS noise, so this is not the main ususpect. With the usual higher order filters inside the SD ADC chips there is no real need for a PLL for the clock frequency. 4% tolerance for the clock would suggest an chip internal RC clock, which is not very good. With a higher order fitler this may still give a resonable mains hum suppression. Still a fixed crystal clock would be the best choice: good enough to get good mains hum suppression and low jitter compared to a PLL. The higher order fitler at the ADC usually also comes with some settling time (e.g. like 60 ms). A very short settling suggest the simple averaging filter and thus not so good mains hum suppression - expecially with the only approximate frequency. It depends on the application which more is more suitable. So the 80 ms settling for the medium rate in the original SW may not be so bad. Ideally I would like to have the choice of the filtering mode to use. |
| 2N3055:
--- Quote from: Kleinstein on December 04, 2021, 09:21:00 am ---Not having an extra AZ mode can happen with the SD ADC chips. The ADC chips internally often do some kind of chopping and have very little drift. If combined with a chopper stabilized input amplifier, there may very well be no real need for an AZ mode. Given a 50 samples per second reading rate the RMS noise is not so bad. The question is more the large span. So the noise seems to be not just white noise, but somewhat different, e.g. with some outliers. I may be worth looking at the noise in the time domain or look at the Allan varaiance. Resudual mains hum would cause a relatively small span compared to the RMS noise, so this is not the main ususpect. With the usual higher order filters inside the SD ADC chips there is no real need for a PLL for the clock frequency. 4% tolerance for the clock would suggest an chip internal RC clock, which is not very good. With a higher order fitler this may still give a resonable mains hum suppression. Still a fixed crystal clock would be the best choice: good enough to get good mains hum suppression and low jitter compared to a PLL. The higher order fitler at the ADC usually also comes with some settling time (e.g. like 60 ms). A very short settling suggest the simple averaging filter and thus not so good mains hum suppression - expecially with the only approximate frequency. It depends on the application which more is more suitable. So the 80 ms settling for the medium rate in the original SW may not be so bad. Ideally I would like to have the choice of the filtering mode to use. --- End quote --- Maybe also an FFT of raw data to see if there are concrete frequencies present or histogram to see distribution. |
| alexvg:
I have tried too many approaches without really relevant success. The best result is the ADC running at 1200Hz or 4800Hz then I resample it at a frequency set by PLL locked to the power-line frequency. The advantage of this method is to have a very large number of samples that can be processed in order to reject noise and get the best measurement value. I've tried realtime multiple transforms (like FFT, MDCT / MDST, wavelet…) but the settling time is too high... CPU power needs is too high… and this reduce the final precision, a little… The processing of detecting and removing all unwanted harmonics is not very simple in realtime. The processor in the DMM is not very powerful and I do not wish to apply a software overclock. Also the AI processing is not possible, yet I thought about it and I would have liked to do it ... In my latest advances I could provide 5.5 digits in 1000V DC range at 1PLC at 50Hz (or 60Hz) - You could look at my previous post with the measurement table. |
| Kleinstein:
There are quite a lot of glitches / far off values in the curve. This may be some spike like background from mains. Another possible cause could be a transfer problem hat the relatively high data rate. The glitches look really bad and make the otherwise good looking curve hard to use. Most of the glitches seem to be periodic with an slightly below 50 units cycle. What are the units ? Using the high data rate and than adjust the sampling interval to the actual mains frequency is a nice idea. Getting averaging over a suitable length interval can get the lowest effective noise bandwidth, but the mains suppression depends on a good frequency match. The SINC³ filter of the ADC directly gives better hum suppression, but more sensitivity to white noise and longer settling. I don't think one would need to do complicated math in the DMM. The main part is some kind of digital filtering, like the simple integration with an adjusted interval. Which fitler is best depends on the application and would ideally be more a user choice. The more complicated analysis may help to find the source of the glitches and maybe decide on how to minize the effect. |
| alexvg:
It's not possible to modify precisely the ADC sampling-rate |O and the ADC frequency drift is very problematic. The curve uses Hz (X) and dB (Y). I use several complex methods (and maths) in order to approach a better measurement value vs simple average (+ internal ADC sinc3 or sinc4). I've found the origin of the main glitchs (230Hz, 457Hz, 557Hz...) but I can't do anything... It's a PCB/schematic problem. About original software : slow-mode or 5 display/sec is equivalent to 40 PLC (at 50Hz) middle-mode or 50 display/sec is equivalent to 4 PLC (at 50Hz) fast-mode or 150 display/sec is equivalent to 1 PLC (at 50Hz) The ADC does a continuous conversion. At 5Hz, with a settling time of 800ms, the overlap is 600ms. The 5Hz measures displayed each second are not independents. Using my processing the overlap is always fixed to 3ms or less and a little pause could be set (if needed) to do a fully independent measures, no overlap at all ! I've checked this at 10PLC using a square wave generator at around 2.5Hz to see 2 totaly different measures (this is impossible in the original software). My goal is to provide the best possible measurement with this limited DMM and a better software. I'm doing my best with the little time I have. |
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