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| Hantek HDG2002B AWG: 5Mhz or 100MHz? Let's see! |
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| Control:Eng:
--- Quote from: tinhead on May 21, 2014, 01:21:55 pm --- --- Quote from: Control:Eng on May 21, 2014, 07:16:05 am ---Hmm...looking at the spectrum...Hantek's design really seems to be imperfect. This is what the AD9747 is capable of: http://wiki.analog.com/_detail/resources/fpga/xilinx/interposer/cf_ad9747_ebz_spectrum_1.jpg?id=resources%3Afpga%3Axilinx%3Ainterposer%3Aad9747 Could somebody maybe explain why we get these spurious spectrums? --- End quote --- two things: on the AD board the SMA is connected directly (except transformer) to DDS, so the spectrum will be worse than on Hantek. And of course when you check what setting they used on SA "span 115MHz/RBW 20kHz" then no wonder that there is nothing visible. There is as well clock aspect, AD is using 250MHz clock on that picture, comming directly from "external source", and you can bet they used good and clean source. With good jitter"free" clock the noise floor is for sure better (and less spurious, but whatever there is, it is not visible due the SA settings). Hantek is using (variable?) clock coming from FPGA (LVDS AC coupled via C191/C187, with DC offset R150/R151). Everything out of FPGA have lot of jitter (minimum 100ps from internal logic pk-pk + pin driver jitter). Such "phase modulated" clock is creating all that spurious and phase noise degradations as shown here: Of course is Hantek using good clock source for FPGA (a bad source would add additional jitter, overloaded external source as well), and some filtering after all, but one will not get better results when clocking with FPGA (they doing this probably to run variable clocks, however if not then one could add clock jitter attenuator from e.g. Silabs to get rid of that jitter. But of course, that extra 20USD or so, one have not to forget that this is not highend AWG). Sure, everything can be done better, and it has been already done, but if one buy gear for nearly price of the compoenents then please don't expect wonder :) --- End quote --- Thank you for clearing things up, tinhead! But now I got some further questions :) What are the main design differences between, let's say an Agilent AWG 33522A (~3000 Dollars) and the HDG2002b (hacked to 30MHz for example). To me, the specs are quite the same. Same sample rate, BW, resolution...is it all about the HW-Design? Is Agilent using other DAC's in their AWG's? Do they have better filters? If I'm right, we get a sin(x)/x attenuation because of the sampling process (correct?). Is there a chance to use an output filter that reconstructs this distortion? I believe that the AD9747 should be quite a performant DAC if used correctly? I don't mind spending some bucks to modify the Hardware of the HDG2002b if the chances are that these efforts could take the HDG to the next performance level. |
| fremen67:
Regarding simple hardware modification, what would you think of an OCXO mod with a Micro Crystal OCXOVT-BV5? Frequency : 10 MHz Power Supply : 5V +/-0.2V Current Consumption : 80 mA max @+30C / 120mA max @-20C Output Level : HC-MOS Compatible Stability vs Temp : +/- 0.15 ppm (-20C to +70C) Stability vs Supply : +/- 0.1 ppm (@5V +/-0.2V) Stability vs Load : +/- 0.01ppm ( @ load +/- 10%) Frequency Tolerance : +/- 0.15 ppm max Control Voltage : +0.5V to +5V DC Frequency Control Range : +/- 4ppm Aging : +/-0.7 ppm max / 1st year Short Term Stability : < 5 E-10 (0.1 s to 30 s) Typical 5 E-11 @ 1 s Phase Noise : 10 Hz: -100 dBc / Hz 100 Hz: -130 dBc / Hz 1 KHz: -140 dBc / Hz 10 KHz: -145 dBc / Hz |
| idpromnut:
@fremen67: Given what tinhead was saying about how the clock is being provided via the FPGA, I doubt a better reference XO will make any difference. In fact the external clock when clocked form a reasonably clean and jitter free source (and I tried three, a Rb and two OCXOs and assuming that the HDG is not mangling this signal too much) had no appreciable difference on quality of the output (if anything it was worse!). |
| fremen67:
--- Quote from: idpromnut on May 22, 2014, 04:07:57 pm ---@fremen67: Given what tinhead was saying about how the clock is being provided via the FPGA, I doubt a better reference XO will make any difference. In fact the external clock when clocked form a reasonably clean and jitter free source (and I tried three, a Rb and two OCXOs and assuming that the HDG is not mangling this signal too much) had no appreciable difference on quality of the output (if anything it was worse!). --- End quote --- OK. It was just because an OCXO option is announced on their website and there is room on the board for that. Of course if the design won't allow any benefit of it, it is useless. Btw did you test the high frequency counter input on your HDG? |
| idpromnut:
--- Quote from: fremen67 on May 22, 2014, 05:31:42 pm --- --- Quote from: idpromnut on May 22, 2014, 04:07:57 pm ---@fremen67: Given what tinhead was saying about how the clock is being provided via the FPGA, I doubt a better reference XO will make any difference. In fact the external clock when clocked form a reasonably clean and jitter free source (and I tried three, a Rb and two OCXOs and assuming that the HDG is not mangling this signal too much) had no appreciable difference on quality of the output (if anything it was worse!). --- End quote --- OK. It was just because an OCXO option is announced on their website and there is room on the board for that. Of course if the design won't allow any benefit of it, it is useless. Btw did you test the high frequency counter input on your HDG? --- End quote --- Not yet; I want to wait for all the ethernet parts + BNC for the HF counter to take the board out once and perform the modifications, rather than pull it out multiple times and strip the case screws (the screws into plastic). |
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