Products > Test Equipment
Hantek HDG2002B AWG: 5Mhz or 100MHz? Let's see!
fremen67:
--- Quote from: tinhead on May 26, 2014, 05:11:48 pm ---
--- Quote from: leppie on May 26, 2014, 04:05:50 pm ---Actually, it seems to be for the 6000 series. You can see it on the Chinese site ... In the specs tab, it notes isolation.
It does come with a faster DSS chip though (500MS/s). Overclocked maybe?
--- End quote ---
AD9783 is pin-compatible 2ch 500MS/s 16bit DAC. Sure it need LVDS instead of LVCMOS interface,
but that not a big deal when using FPGA to provide the data. So to get HDG6xxx one need new DAC,
some passives, isolation PCB (what so ever they used for), OCXO and firmware dump from such AWG.
The PCB label shows HDG2000 and not HDGx000, but that might be coming from late decision etc.
So yeah, HDG6000 might really be using same PCB/PSU.
--- End quote ---
At least the firmware won't be too different from the one in our HDG as it already knows the HDG6162B. If you use this name, the sinus waveform is unlocked up to 160Mhz ;), exactly what is described on the Hantek site...
As the FPGA is configured through a file (/lib/firmware/htg1000.bit) we could imagine that this file could be enough for the software mod ... or at least not far.
fremen67:
Another thing regarding the potential HDG6xxxx mod.
When set to HDG6162B, the output of the HDG2000 is divided by 2. A 160Mhz Sine set on the HDG shows at 80Mhz on the scope. This would be compatible with a DAC 2xfaster and the HDG firmware adapting the FPGA output to the DAC to reach the "supposed" correct sampling rate of the AD9783... am I wrong?
This also would mean that the current firmware knows more than only the HDG6xxxx max input frequencies.
What do you think?
FrankenPC:
Playing with the signal generator finally...I got my Rigol back from repair. So, I don't see any impedance compensation option. There is none right?
Anyway to check for firmware updates? Is there a Hantek firmware site? This thing locks up in really weird ways.
fremen67:
--- Quote from: FrankenPC on May 30, 2014, 02:03:48 am ---Playing with the signal generator finally...I got my Rigol back from repair. So, I don't see any impedance compensation option. There is none right?
--- End quote ---
Didn't see any option. It seems to be 50 ohms.
--- Quote from: FrankenPC on May 30, 2014, 02:03:48 am ---Anyway to check for firmware updates? Is there a Hantek firmware site? This thing locks up in really weird ways.
--- End quote ---
This the link: http://www.hantek.com/en/ProductDetail_149.html but no update at the moment, and yes it would definitely need one.
All of you having a HDG, could you post your software and hardware version? I think it will be faster to update with a backup of one of us when it is a new one. Mine are:
Software 1.00.1 (140402.0)
FPGA 11
PCB 1002
tinhead:
--- Quote from: fremen67 on May 27, 2014, 08:41:43 pm ---When set to HDG6162B, the output of the HDG2000 is divided by 2. A 160Mhz Sine set on the HDG shows at 80Mhz on the scope. This would be compatible with a DAC 2xfaster and the HDG firmware adapting the FPGA output to the DAC to reach the "supposed" correct sampling rate of the AD9783... am I wrong?
--- End quote ---
yes, that make sense.
--- Quote from: fremen67 on May 27, 2014, 08:41:43 pm ---This also would mean that the current firmware knows more than only the HDG6xxxx max input frequencies.
What do you think?
--- End quote ---
the firmware have multiple binaries, hard to follow what/where is responsible for what. But assuming they too lazy,
the firmware (ARM part of it) will be able to control HDG6000 as well. The question is, where these 160MHz has been defined.
If in ARM firmware (and DDS firmware in FPGA is talking whatever ARM is sending), then one have to find it and patch, to e.g. 200MHz. Here is of course extra aspect - dds output is not everything, how is then the rest of hardware at 200MHz?
It can be as well that the FPGA firmware for HDG6xxx is different. But maybe there is way to check it. When you have
changed your AWG to HDG6xxx, and set 160MHz clock (probably it will be work in lower clocks as well, but let try the limit to ensure that no other option, from lower models, has been trigered), then you can measure the DAC clock. If the FPGA design is universal, you will see here 500MHz. This will be probably too much for the DAC and it will cloock on every second edge, so 250MHz.
But when you see 250MHz on DAC clockin, then the FPGA design is not universal and it is simply trying to set something based on control code from ARM fw.
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