Products > Test Equipment
Hantek HDG2002B AWG: 5Mhz or 100MHz? Let's see!
Stevie1966:
:bullshit:AD9747BCPZ,very good.
high dynamic range, dual digital-to-analog converters (DACs) with 16-bit resolutions and sample rates of up to 250 MSPS.
http://www.analog.com/en/digital-to-analog-converters/high-speed-da-converters/ad9747/products/product.html
flatlander:
Got my HDG2002B today. System info below, FPGA version seems to have jumped a few versions.
Software: 1.00.2 (140926.0)
Kernel: Linux 3.2.35
FPGA: 20
Keyboard: 3
PCB: 1004
idpromnut:
--- Quote from: flatlander on October 20, 2014, 09:48:12 am ---Got my HDG2002B today. System info below, FPGA version seems to have jumped a few versions.
Software: 1.00.2 (140926.0)
Kernel: Linux 3.2.35
FPGA: 20
Keyboard: 3
PCB: 1004
--- End quote ---
Nuts, now I really wish I could get a firmware upgrade for my unit :'(
Cyber7:
Mine arrived last Saturday. I don't have the 5080 for the hi-req counter yet, but I've added the Ethernet components successfully. Ping works! :-+ Of course, there is only bare transport support at the moment. Now, maybe I can work out a proxy ala VXI for SCPI commands to the USB IF. Hmmm.... I'd love to use it with Agilent IO via tcp. Haven't tried the direct route yet via USB using Agilent drivers. Anyone have any luck this route?
Software: 1.00.2
Kernel: Linux 3.2.35
FPGA: 14
Keyboard: 3
PCB: 1004
I am keeping a blog at http://hdg2002b.simplesite.com . So far I have consolidated all documentation I have: datasheets, hi-res scans & pics, scripts and upgrade procedures sourced and credited to the fine folks that have contributed to this forum. :clap:
The firmware partitions for 1.00.2 are not the same as 1.00.1. They added a recovery partition. I updated the nanddump script for the new geometry, and succeeded with dum pin mtd0 to mtd8. I have successfully JTAGed the s3c2416 and NAND with a cheapo 100ask.net USB adapter via openocd. The scripts for USB nandbackup and the openocd config for the AWG target is attached below, and posted on the above site. Rename the .txt file as .cfg.
I also removed the heatsinks on the outputs and identified the part as a TDS3091. I've worked out a schematic of the output on Multisim...though, it's not yet functional. I've made some assumptions on caps/inductors. I applied Stevie1966's fix for the outputs. I can confirm that it does remove the ringing from the under-dampened input to the TDS3001 amp stage at >=4v output. :-+ THANKS! :-+ I've yet to verify that it hasn't altered the amplitude, but it looks good, albeit somewhat over dampened.
Cyber7:
@FLatlander: Could you post your FPGA bin file? I'd be interested to see if they have done anything about the jitter that gets really bad above 5mhz for the standard waveforms.
Insert a fat32 USB stick and copy the bin file to the stick via this shell command over the serial port:
cp /dso/lib/firmware/* /mnt/udisk
zip the htg*.* files and post it here.
I've attached mine below. Note that the binary header for the file contains some useful info, including the device family "6slx16csg324", which is a Spartan-6 LX FPGA (XC6SLX16-CSG324) and the compilation date/time: 2014/06/15 10:01:28
"AFG3050.ncd;HW_TIMEOUT=FALSE;UserID=0xFFFFFFFF.b..6slx16csg324.c..2014/06/15.d..10:01:28"
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