Products > Test Equipment
Hantek HDG2002B AWG: 5Mhz or 100MHz? Let's see!
alex.forencich:
--- Quote from: idpromnut on October 26, 2014, 02:26:16 am ---Where should that new thread go, in testgear or projects?
--- End quote ---
Dunno. Not sure which one would make more sense.
idpromnut:
I'll create one in testgear for the moment, since the bulk of the immediate work would be to figure out how to build a new firmware base for the unit. It can always be forked into different threads at that point depending if other people want to build on that base image to do different firmwares.
flatlander:
Did some testing on my 'upgraded' Hantek HDG2002B and found that the amplitude of the generated signal (sine) quickly drops off past 5MHz. It seems that my unit's firmware is still limiting the bandwidth to 5Mhz even though it lets me increase the frequency to 100Mhz. I tried loading older FPGA firmware but that doesn't work at all (no output and all output related self tests fail). Possibly have to flash a 'matching' set of software and FPGA versions. I'd be interested to know if the amplitude issue also exists on earlier software/hardware versions.
Versions:
Software: 1.00.2 (140926.0)
Kernel: Linux 3.2.35
FPGA: 20
Keyboard: 3
PCB: 1004
PS: alex.forencich and idpromnut thanks for kicking off an open source initiative for this generator. I'll help where I can.
alex.forencich:
--- Quote from: flatlander on October 26, 2014, 09:42:24 am ---Did some testing on my 'upgraded' Hantek HDG2002B and found that the amplitude of the generated signal (sine) quickly drops off past 5MHz. It seems that my unit's firmware is still limiting the bandwidth to 5Mhz even though it lets me increase the frequency to 100Mhz. I tried loading older FPGA firmware but that doesn't work at all (no output and all output related self tests fail). Possibly have to flash a 'matching' set of software and FPGA versions. I'd be interested to know if the amplitude issue also exists on earlier software/hardware versions.
Versions:
Software: 1.00.2 (140926.0)
Kernel: Linux 3.2.35
FPGA: 20
Keyboard: 3
PCB: 1004
PS: alex.forencich and idpromnut thanks for kicking off an open source initiative for this generator. I'll help where I can.
--- End quote ---
I think there is a filter in the output stage that you need to bypass in order to get full bandwidth. There are details here somewhere...
alex.forencich:
Reverse engineering thread is here: https://www.eevblog.com/forum/testgear/hdg2002b-awg-firmware-reverse-engineering/
I have managed to back out most of the pins going to the FPGA and create a partial UCF file. The only ones left (that I can tell anyway) are the DDR2 SDRAM pins. I have not figured out how I am going to probe those quite yet; it's not so easy to probe under a BGA.
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