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| Hantek 4032L Logic Analyzer |
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| Scratch.HTF:
With reprogramming of the FPGA SPI flash (MX25L4005) via JTAG (/WP can only be controlled via JTAG - the flash cannot be programmed or even read via the SPI header even with the Reset jumper closed according to my experience), the following functions can be possible with modified host software: * Data compression as in the SysClk LWLA1034 (and others) * Qualifier capability (record data only on qualifying conditions) * If-Then-Else sequencer with full conditional structure (up to a certain number of levels) * Multiple state trigger words * Range recognizer * Selective data acquisition functions * Programmable STOP conditions * 64 bit (probably shorter) FIFO stream trigger (good for triggering on I2C and SPI) * Option to combine logic ports to extend number of points (e.g. 32-16-8-4-2-1 bit for 64M-128M-256M-512M-1G-2G points) From what I know, the Cypress FX2LP core has the ability to directly edit the data contents of the internal 16 KByte RAM and the internal 512 byte scratchpad RAM via a vendor specific command defined in the boot ROM for "soft" user code downloads. JP2 (FPGA JTAG) 1 GND 2 TMS 3 TDO 4 TDI 5 TCK 6 +3.3V JP6 (FPGA Reset - may need to leave unshunted to enable external reading/writing of FPGA SPI Flash via JTAG) 1 /RESET 2 GND JP7 (FPGA Flash SPI) 1 +3.3V 2 SCK 3 SI 4 SO 5 /CS 6 GND All pins have 4K7 pullups to +3.3V. I will provide images of the Cypress FX2LP boot ROM (24LC64) and FPGA flash (which may be tied to a particular Xilinx DeviceDNA ID) on request. |
| abyrvalg:
Scratch.HTF, WP# is on separate JP5 (close to drive high). All SPI signals are connected to FX2 also - this can be the source of your r/w problems. Reading the flash via FX2 works fine (see my sources above). |
| Moskvoshveya:
I'm sorry, but have you any sample FPGA project, which is using memory, soldered on this board? I want try to make own firmware (of course, for add compression), but have no experience with Xilinx Core generators. Using already built DDR2 core will helps to save time by skipping MIG investigation. FX2LP and other things are not a problem. Most problem is Xilinx Based tool because all my experience is Altera based. |
| lfldp:
hello have one question , does this hantek 4032L have trigger out functionallity ? regards |
| meandeev:
sorry for reviving this old thread, but I got a half-dead (doesn´t connect to the pc via USB). So I desoldered U3 (24L64, fx image), saved the old data and flashed the data from #28 with an external programmer. But after that the LED no longer lights up! And also no USB connection... The LED´s works again after switching back to my saved data. I switched the data once more to be sure that I didn´t make an error. Same result. If one compares both images, one can find missing byte here and there in the data from #28 - because of reading the data via USB? So is there an error in #28? The LED is driven by the fx (pin92=PE6 and pin91=PE5). So here my U3 fx data is attached (desoldered and read with an external programmer) PS: reading U8 (fpga data stream) with an external programmer give the same data as in #28 |
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