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| How good of a DMM or Oscope could you make with modern CPU or GPU ? |
| (1/5) > >> |
| MathWizard:
If you take any top CPU or GPU chip, like a 12900k or rtx3090 (a lot more than just the chip), and set them up to work as the core of a DMM or oscilloscope...not in windows, I mean if u designed the DMM/scope with ^^ as the core. How good could they be ? They all love crunching numbers, but I know CPU's and GPU's don't work exactly the same, nor do DMMs and scope's. |
| ataradov:
For DMM it would be a total overkill. A regular MCU is plenty for even the most advanced DMM with graphics capabilities. For the scope - sure, why not? Replacing windows does not buy you much, so you might as well keep it (or replace with Linux, or any other OS). All you need to do in this case is a PCI ADC board. But this is not new, scopes were designed like this for decades. You won't get a huge boost in practical performance though. Modern design with SoC+FPGA is pretty optimal. If anything, performance is much better scaled with a larger FPGA or a secondary SOC to drive the UI independent from the acquisition. And power consumption of that PC would be though the roof. And EMI would be a nightmare as well. |
| David Hess:
DMM sample rates are not high enough to require that sort of processing power. Even at thousands of high resolution samples per second, real time FFTs can be done with a battery powered embedded processor. We already have modern DSOs which use that sort of processing power to generate real time displays at 10s of gigasamples per second. At a lower sample rate, decimation could be done by the processor in real time instead of an FPGA. The chief limitation on performance is level 1 and level 2 cache bandwidth with the record size likely limited to a large fraction of the level 2 cache size. |
| robert.rozee:
i suspect the original poster is thinking of something like this, scaled up: https://www.eevblog.com/2019/11/13/eevblog-1260-70-100mhz-oscilloscope/ ie, simple front-end, cheap ADC, and a processor with heaps of grunt to do all the heave lifting. in a dense, a bit like how an SDR (software defined radio) works where the analog hardware in minimal and computing power handles everything else. re-framing the question: given a modern-ish CPU coupled closely to an ADC and a low-complexity front-end, what sort of actual performance could be attained; what would be the realistic top sample rate, and realistic bandwidth? lets say one started with a Raspberry Pi 3 for instance, and add on a PCB containing 2-channels of input and a pair of ADCs with a maximum parts cost of, say $20. what could be achieved? cheers, rob :-) |
| ataradov:
You can develop all sorts of theories of what could be done with this architecture, but you wont get anywhere close to the performance of the low end "real" scope. The most significant performance bottle neck (even in the case of that FNRSI scope) is getting the samples into the memory and processing them for a trigger condition. Once trigger is found you can take your time processing the data. Performance of the x86 does not help here at all. You have to "look" at all samples. And cheapest FPGA would do that on the fly with no additional overhead. And in case of the RPi your first issue would be how to get the samples into the memory. 40 pin connector does not have any interfaces that would be fast enough. Camera interface may be abused for that, but the performance would be pretty limited still. |
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