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| How to detect invidual load across parralled MOSFETS |
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| SpottedDick:
--- Quote from: Berni on July 01, 2022, 05:26:38 am ---Just add shunt resistors to ground for each transistor. They will not only let you see the current but also give each transistor its own mini feedback loop that balances the current across all of them. The more current the transistor draws the more voltage drops appears on the resistor, this lifts the transistors pin up so that the gate sees less voltage, closing down the transistor so its current reduces. --- End quote --- That's an interesting idea for the modded DL24 I have, but looking at the shunt (0.05 Ohm), I'd only be dropping 0.05V at 10A across the whole array, so I doubt that would make a significant difference. |
| switchabl:
Well, yes, this circuit clearly is a bad idea and I believe the OP already knows that. So assuming this is mostly about the educational value ("I really want to see just how bad it is") and at the risk of stating the obvious: a current probe should work. I assume the DUT is the one from the other thread (https://www.eevblog.com/forum/testgear/example-of-why-people-say-you-sholdnt-use-mosfets-in-parrallel-as-dummy-load/msg4247347/#msg4247347), with point-to-point wiring between the MOSFETs. In this case, just about any clamp-on-style probe or even clamp meter (that goes to DC) would work. In a more conventional circuit, you might have to resort to something like an I-Prober. |
| Berni:
--- Quote from: SpottedDick on July 01, 2022, 10:42:42 am --- --- Quote from: Berni on July 01, 2022, 05:26:38 am ---Just add shunt resistors to ground for each transistor. They will not only let you see the current but also give each transistor its own mini feedback loop that balances the current across all of them. The more current the transistor draws the more voltage drops appears on the resistor, this lifts the transistors pin up so that the gate sees less voltage, closing down the transistor so its current reduces. --- End quote --- That's an interesting idea for the modded DL24 I have, but looking at the shunt (0.05 Ohm), I'd only be dropping 0.05V at 10A across the whole array, so I doubt that would make a significant difference. --- End quote --- That still means the too exited transistor hogging most of the current gets 50mV less drive signal on the gate, turning it on slightly less so it lets the other transistors do more of the work. If 50mV is enough is a question of what kind of FET it is. For transistors with a very sensitive gate that can conduct a fair bit of current already at 1.5V gate voltage, then taking away 50mV can mean quite a bit. For particularly insensitive transistors that need something like 7V to pass any reasonable current those 50mV is not much. The point is that you choose a shunt resistor value that is reasonably small, yet at the same time still large enough to stabilize the transistors behavior. You can use these resistors to actually measure the imbalance in current sharing and see if it is working well. To give it a worst case scenario you can intentionally loosen one of the transistors on the heatsink, letting it get hot, so that its characteristic drifts particularly far from the others, if it can still current share reasonably well when its 50°C above others then it will work fine for pretty much all cases. |
| t1d:
I also researched a similar balancing topic and found the possible methods to be much more broad than I had anticipated. In addition to balancing with resistors, there are other methods/components... For example, diodes. Each method has its own pros and cons. In addition to passive methods, there are all sorts of active methods that work on feedback... arrangements of transistors, op amps driving transistors/MOSFET/Etc. Just for your considerations in learning, attached is a circuit I adapted from an EDN design. As I used it as a learning tool, it may, or may not be exactly correct. But, it will surely give you some ideas to broaden your thinking... The link to the EDN design is on the schematic sheet, in the information block. I have my original KiCad files, if someone wants them. I also had proto PCB boards manufactured. They are incorrect, but they can be bodged. I would be glad to share them, if anyone wants to send me a private message. I can't remember if I corrected the schematic, after I discovered the boards were faulty. I would have to check, but it is rather likely. I do not want to high-jack the OP's thread with comments about the circuit. If someone wants to discuss it, please let me know and we will move to a separate thread. Anyway, my point is to suggest that you research different load leveling methods. They generally will include some method of reading the load on each path. |
| RCinFLA:
Some info that might be of interest on DL24P with addition for extra load devices. |
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