New progress. I started playing with an Altera Cyclone 2 FPGA, mainly to improve my Verilog.
I don't know how other learn but for me, it's hard to learn without having a real project so I thought why not make something useful and learn in the process.
Enough ranting, let me tell you what I found.
The development boardI started with playing with an Altera DE1 development board from Terasic. I modified their VGA Verilog example, which was set to output 640x480, to 1024x768 60Hz. Then I started playing with the VGA parameters changing the pixel clock, sync timing, back and front porch, etc.
To my surprise, the 5" and 5.6" LCD modules that I bought from ebay are very tolerant with non standard timing, they auto adjust pretty much to almost anything I throw at it... well, within reasonable limits, and where three normal monitors display either "out of range" or an incomplete image.
The PAL input signalThe next step was to analyze the PAL, NTSC and DEFAULT sync on my HP8591E and this is what I found. I will only show the PAL specs because that's the one that is of interest at this point, it gives me numbers that I can work with to generate the correct frame rate for VGA.
Pixel clock - 21MHz
H Sync - 96 pixels
V Sync - 3 lines
Line total - 1352 pixels
Frame - 312 lines
Active line - by my calculation 508 pixels but it may be 512 pixels
Active lines - 254 lines
Horizontal and vertical front and back porch are variable with the vertical and horizontal position.
Line time - 64.38us
Frame time - 20.087ms
I also analyzed the two digital circuits that make the two level video output. I named them PIXEL and INTENSITY lines. The PIXEL line goes high every time a pixel is displayed on the CRT, the INTENSITY line stays high if a high intensity pixel is displayed and goes low for low intensity. Scope screen shot attached.
The VGA sideOk, so now knowing that the LCD is tolerant to non standard timing, I played with the FPGA PLL with 21MHz input clock to see if I can find any timing combination that would give me the same frame time at the VGA output. And bingo! A pixel clock of 55.125MHz, 1352 pixels and 819 lines gives me the same frame time. These numbers are total numbers, visible is still 1024x768. Why do I want the same frame time? This simplifies a lot the frame buffer size and BOM.
I have enough RAM in the Cyclone 2 and up FPGA to implement a half frame, 2 bit, dual port frame-buffer so I don't need external RAM.
To reclock the 512x254 PAL image to 1024x768 VGA, I only need to sample, encode and store every pixel (2 bits, pixel and intensity) and then read back and display every PAL pixel to 2 VGA pixels horizontally, and every PAL line to 3 VGA lines vertically. It's up to the LCD driver chip to render the image.
The pixel clockAs I said, the PAL pixel clock is 21MHz but I would need to wire it to the FPGA somehow and then generate the 55.125MHz in the FPGA PLL. Another solution is to regenerate it from the H Sync. For that I can use ICS9173B and that is exactly what the Symmconn labs guy is using. Sure his project is much more elaborate, from what I see it accepts all three modes and drives the LCD directly, outputs a VGA, etc, so it must be a real up-converter but I'm not there and I think my solution would work.
What do you think about this idea? Any draw backs that you can see? This can translate into a reasonably priced community project to replace the CRTs on these oldies but goldies.
I know many think the green CRTs are better but adding a bit of colour for the right price, may be tempting for some.
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