HP 8594E Replacing the green CRT with LCD

[Miti]

One may be the caps failing a it takes a while to actually display anything on the CRT plus the whole image starts very large & unfocussed before settling down to a nice sharp & bright image.

The other is a dead CRT unfortunately. Thanks for the suggestion.

Phil

Yes, that is typical  dry caps symptom. You replace them with some good quality caps and you  give it another 10+ years.

[Miti]

I'm having a similar issue with an LCD monitor on the composite video output of my Anritsu MS-420K. The image on the LCD is shifted up and to the right, clipping off the top line of the display. The Super Circuits LCD measures 5.6" diagonal. Sadly, its menu has no adjustments for size or position.

I've emailed several sellers of LCD panel+controller combos on eBay, asking if their unit offered those adjustments. They all said no.

What about the instrument itself. Does it have horizontal and vertical adjustments like HP8590E series have?

[precaud]

It has them, but unfortunately they don't affect the external composite output, only the internal.

[Miti]

I want to revive this topic. I think I found a reasonable solution from the cost and complexity perspective.
After I saw the Simmconn Lab's board (manual attached), I wanted colour. I wanted to find a simple solution to have a green graticule and yellow trace.
I know that my 5" AV LCD can synchronise when HP8591E is set to PAL video. I tried to separate the low and high brightness of HP8591 and feed them to green and red of an AD722 encoder, then feed the output CVBS to the LCD. The image is fuzzy and has relatively low resolution while there's colour crawling across the screen that is unacceptable. Screen shot attached.
Then I came back to directly driving the LCD from the SA video, I reduced the half brightness of the A16 video output by adding a 390 Ohm resistor in parallel with R301, as described in the same attached manual.
I then raised the output black level by about 250mV to make room for the sync pulses and added two transistors for HS and VS.
The result is shown in the attached simulation file, just rename the txt to asc.
Everything on the left of R13 is on the A16 board. R13 and everything on the right is my circuit.
The result is a B&W, very sharp image, with two levels.
Pictures and pros and cons in the next post.

[Quarlo Klobrigney]

What kind of lead length do you have running from one area to another? Do you have a photo of the overview of the connections? The text file is wire here and there. Is that supposed to be a schematic layout? One more thing is there any coaxial running in there or are you doing plain wire. Plain wire is leaky. Coaxial is lossy and needs a DA.

[Miti]

Here are some pictures with the result.

Pros:
* Cheap, the LCD can be bought on ebay for less than $50 and the rest is peanuts
* Not very invasive, you only add a resistor to the A16 board, everything else is external
* We have a solution to recover a SA with a dead display. A solution that costs 350 USD, is hard to justify for me.

Cons:
* No colour or at least green colour (even though it may be a solution. Modify the LCD driver to drive the green colour only, AKA shorting R and B lines to GND)
* Does not align perfectly to the plastic frame. The image fills the screen horizontally but it's a bit compressed vertically.
* No dimensional control. 5" is a bit small, 5.6"would fit better vertically but would go out of the frame horizontally, by my calculation.

[Miti]

And a picture with the frame and smoky screen.

[Miti]

The text file is wire here and there. Is that supposed to be a schematic layout?

It is an LTSpice .asc file. Change the extension to .asc and open it in LTSpice.

[Quarlo Klobrigney]

I thought this was with something that you were cobbling together that resulted in lack of high frequencies. I am confused.

Don't have LT Spice.

[Miti]

Don't have LT Spice.

It’s free software, very useful. You can download it.
Or I can take a screenshot and post it later.

Edit: Added schematic screenshot.

[Quarlo Klobrigney]

As long as they don't need a lot of info and my first born!

[madao]

What is typ of display ?

Here ?
https://www.ebay.de/itm/New-5-6-5-6inch-640-480-TFT-LCD-VGA-RGB-AV-Module-Display/121194129870?hash=item1c37bba9ce:g:sFgAAOxyWt5SW1Sm

[Miti]

What is typ of display ?

Here ?
https://www.ebay.de/itm/New-5-6-5-6inch-640-480-TFT-LCD-VGA-RGB-AV-Module-Display/121194129870?hash=item1c37bba9ce:g:sFgAAOxyWt5SW1Sm

There’s a link to the one that I bought in ones of my previous posts. As I said, 5.6” may go out of the frame horizontally.

[Miti]

I experimented a bit more with the LCD by manipulating the color bus. The result is, I can make separate colors for the low and high intensity.
Below is the result of grounding the low nibble of the red bus and connecting the high nibble to the MSB of the driver through the 4 x 33 Ohm resistors.
This way I can have yellow, cyan or magenta grid and menus. Trace is always white.

[Miti]

New progress. I started playing with an Altera Cyclone 2 FPGA, mainly to improve my Verilog.
I don't know how other learn but for me, it's hard to learn without having a real project so I thought why not make something useful and learn in the process.
Enough ranting, let me tell you what I found.

The development board

I started with playing with an Altera DE1 development board from Terasic. I modified their VGA Verilog example, which was set to output 640x480, to 1024x768 60Hz. Then I started playing with the VGA parameters changing the pixel clock, sync timing, back and front porch, etc.
To my surprise, the 5" and 5.6" LCD modules that I bought from ebay are very tolerant with non standard timing, they auto adjust pretty much to almost anything I throw at it... well, within reasonable limits, and where three normal monitors display either "out of range" or an incomplete image.

The PAL input signal

The next step was to analyze the PAL, NTSC and DEFAULT sync on my HP8591E and this is what I found. I will only show the PAL specs because that's the one that is of interest at this point, it gives me numbers that I can work with to generate the correct frame rate for VGA.

Pixel clock - 21MHz
H Sync   - 96 pixels
V Sync - 3 lines
Line total - 1352 pixels
Frame - 312 lines
Active line - by my calculation 508 pixels but it may be 512 pixels
Active lines - 254 lines
Horizontal and vertical front and back porch are variable with the vertical and horizontal position.
Line time - 64.38us
Frame time - 20.087ms

I also analyzed the two digital circuits that make the two level video output. I named them PIXEL and INTENSITY lines. The PIXEL line goes high every time a pixel is displayed on the CRT, the INTENSITY line stays high if a high intensity pixel is displayed and goes low for low intensity. Scope screen shot attached.



The VGA side

Ok, so now knowing that the LCD is tolerant to non standard timing, I played with the FPGA PLL with 21MHz input clock to see if I can find any timing combination that would give me the same frame time at the VGA output. And bingo! A pixel clock of 55.125MHz, 1352 pixels and 819 lines gives me the same frame time. These numbers are total numbers, visible is still 1024x768. Why do I want the same frame time? This simplifies a lot the frame buffer size and BOM.
I have enough RAM in the Cyclone 2 and up FPGA to implement a half frame, 2 bit, dual port frame-buffer so I don't need external RAM.
To reclock the 512x254 PAL image to 1024x768 VGA, I only need to sample, encode and store every pixel (2 bits, pixel and intensity) and then read back and display every PAL pixel to 2 VGA pixels horizontally, and every PAL line to 3 VGA lines vertically. It's up to the LCD driver chip to render the image.

The pixel clock

As I said, the PAL pixel clock is 21MHz but I would need to wire it to the FPGA somehow and then generate the 55.125MHz in the FPGA PLL. Another solution is to regenerate it from the H Sync. For that I can use ICS9173B and that is exactly what the Symmconn labs guy is using. Sure his project is much more elaborate, from what I see it accepts all three modes and drives the LCD directly, outputs a VGA, etc, so it must be a real up-converter but I'm not there and I think my solution would work.

What do you think about this idea? Any draw backs that you can see? This can translate into a reasonably priced community project to replace the CRTs on these oldies but goldies.
I know many think the green CRTs are better but adding a bit of colour for the right price, may be tempting for some.

[Gandalf_Sr]

Miti,

I think your project is a great idea.  The CRT is a big issue on a lot of the older HP/Agilent/Anritsu high end gear.

[Miti]

A lot happened from my last post. With BIG help from the community, and special thanks to BrianHG, I have the best video genlock circuit to generate the 21(42)MHz video sampling clock and the 55.125MHz VGA clock without any external components, everything is done inside the FPGA.
I have figured out how to convert the analog input video with two levels of brightness in a digital two bits, using only two differential inputs.
There's also the I2C ADC to read the brightness potentiometer, which I think can be improved/simplified since I don't really care much about linearity, resolution, etc.

All these experiments are here:

https://www.eevblog.com/forum/projects/modern-equivalent-of-74hc4046-pll/
https://www.eevblog.com/forum/fpga/converting-a-two-level-analog-signal-to-two-bits-digital-in-cyclone-iv-orand-v/
https://www.eevblog.com/forum/fpga/adc-in-altera-cyclone-fpga/

The project continues...

[Miti]

Almost there, I have to figure out a bug in the code that generates the write address and why a vertical line towards the right side is completely missing.
Unfortunately the pictures don't tell the full story. The real thing is way more vivid than the pictures show. The color themes choices are unlimited.

[BrianHG]

Looks like my 'insane' idea of having an IO pin drive a clock input pin to feed the second FPGA pll works.

[Miti]

Looks like my 'insane' idea of having an IO pin drive a clock input pin to feed the second FPGA pll works.

Yes, it does and it saved me a lot of pain, thanks!

I can't figure out what is wrong with that line missing on the right side of the image, see those partial characters in the right hand menus. Address is there, wrEN and sample pulse are there, the line is not. And no, it is not the LCD module or the code. All I can think of is that it is the reason why this FPGA is marked EP4CE6 and not EP5CE10. Remember, I'm using an FPGA marked EP4CE6  as EP4CE10 and it mostly work. There must be something wrong with writing to certain addresses.
The memory initialization file is displayed correctly though, but I guess there's back door to do that, not through direct addressing.

[bsdphk]

If the HP uses a standard CRTC chip, for instance a 6845 or similar, you could also hack the firmware to change the video format.

Many HP instruments have undocumented memory read/write commands which would make the process pretty easy.

[MarkL]

If the HP uses a standard CRTC chip, for instance a 6845 or similar, you could also hack the firmware to change the video format.

Many HP instruments have undocumented memory read/write commands which would make the process pretty easy.

Here's an extract from a post on the HP/Agilent/Keysight group.  I don't know the address range for the video controller but it can probably be figured out from the schematic...

Here are the GPIB commands for the 8590 series:

  MRDB <addr> - returns single byte in decimal
  MRD <addr> - returns single word in decimal
  MBRD <addr>,<count>  - returns a block of memory in binary

<addr> and <count> are in decimal.  The SRAM is 524288 (0x80000) bytes long and starts at 0xf80000.  It's a Motorola processor, making storage big-endian.  I/O is memory mapped, so there's a lot to explore outside the SRAM range.

For write, I found the commands MWRB, MWR, and MBWR.  No doubt these are the analogous operations for writing, but I did not experiment with them.

For example, the model number exists at 0xffbfee, 16760814 decimal, and is stored as decimal ("spq" below is a local Linux utility that sends a string to the scope's GPIB interface and returns the result):

  $ spq MRD 16760814
  8595

And after that, the next byte:

  $spq MRDB 16760816
  69

69 is decimal for "E" --> "8595E".

[BrianHG]

Looks like my 'insane' idea of having an IO pin drive a clock input pin to feed the second FPGA pll works.

Yes, it does and it saved me a lot of pain, thanks!

I can't figure out what is wrong with that line missing on the right side of the image, see those partial characters in the right hand menus. Address is there, wrEN and sample pulse are there, the line is not. And no, it is not the LCD module or the code. All I can think of is that it is the reason why this FPGA is marked EP4CE6 and not EP5CE10. Remember, I'm using an FPGA marked EP4CE6  as EP4CE10 and it mostly work. There must be something wrong with writing to certain addresses.
The memory initialization file is displayed correctly though, but I guess there's back door to do that, not through direct addressing.

Share your code.  A lot of beginners in HDL miss things easily when synchronizing buffers, address counters & data chains and write enables for internal FPGA ram.  It gets worse when reading since there is a 2 clock delay from control input to data output.

[Miti]

Share your code.  A lot of beginners in HDL miss things easily when synchronizing buffers, address counters & data chains and write enables for internal FPGA ram.  It gets worse when reading since there is a 2 clock delay from control input to data output.

In the end, the issue was in my code. I didn't like it anyway so i rewrote it. See below the result.
The only reason why I hesitate posting my code is that "OMG, what a crappy code" anticipated reaction from you, the HDL gurus, which I dread .
The new code, even though it (mostly) works, still needs some clean up.

Edit: One thing that I found out, it doesn't matter if the frame rates are different between the input and output, I don't see a thing in the image, so I reverted to standard VGA 1024x768 @60Hz (well almost 60Hz, I can't get 65MHz from the output PLL, I get 64.909091MHz but it is close enough). Now I need to make the board.

[Miti]

One positive side effect of using Brian's idea of digital PLL with DDIOs in the FPGA is that it doesn't need a feedback clock divider as it would if I used MK9173, for example. That means that as long as the HSync pulse is aligned with 4x the 42MHz clock, it would generate the correct 42MHz frequency regardless of the front porch, back porch or active pixels on the line. That means it should work in all 3 video modes that HP8590 can output, NRM, PAL and NTSC. And it does, see below. It's getting better and better.