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HP Logic Analyzer Inverse Assemblers

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gslick:

--- Quote from: Hamster on March 12, 2024, 03:17:13 pm ---also looking at the 80186 ( which is one i just picked out of thin air ) , seems Stat/CoProc/Dma Ch all use the same A5 Pod..  but no A4.. so POD4 shouldn't do anything on the IA module.

--- End quote ---

I haven't found a full manual for the 64658A 10306B 80186/80188 Interface yet, which should have full details on the POD signal connections.

There are manuals available for some of the other preprocessor interfaces, which have full details on the POD signal connections. For example:

64657B 10312D 80286 Preprocessor Interface
http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/10312-90911_10312D_80286_Preprocessor_Operating_Manual_198902.pdf

E2409B 80286 Preprocessor Interface
http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/E2409-90903_E2409B_Intel_80286_Preprocessor_Interface_Users_Guide_Feb92.pdf

10314D 80386DX Preprocessor Interface
http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/10315_90915_10314D_Intel_80386DX_Preprocessor_Interface_Users_Guide_199202.pdf

Hamster:
I have the Manuals for the z80, 68000 I will try to scan them when i put my hands on them, it has all the pin information in them.

Obviously this isn't needed for the _P IA Options ( non pre-processor )

gslick:

--- Quote from: Hamster on March 12, 2024, 08:58:39 pm ---I have the Manuals for the z80, 68000 I will try to scan them when i put my hands on them, it has all the pin information in them.

Obviously this isn't needed for the _P IA Options ( non pre-processor )

--- End quote ---

These two manuals have full schematics for the 64683A 10300B Z80 and 64670A 10311B 68000 Preprocessors:

http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/64683A_Z80_Interface_Module_Service_Brief_6483-90901_Jan_1983.pdf

http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/64670A_68000_Interface_Card_Service_Brief_64670-90901_Dec_1982.pdf

If anyone is curious, with preprocessor schematics and the Signal Routing tables B-1 and B-2 in the 10269C manual it can be seen exactly how the signals from the target microprocessor route though the preprocessor and the 10269C to the logic analyzer POD connections.

http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/10269-90910_General_Purpose_Probe_Interface_Aug87.pdf

Hamster:
Based on what i see...

For Z80...  I assume State Machine Mode.. Rising Edge on CLK0 for Qualifier? or Falling Edge?

ADDR

A0  - J4 1 - POD 2 / 0
A1  - J4 2
A2  - J4 3
A3  - J4 4
A4  - J4 5
A5  - J4 6
A6  - J4 7
A7  - J4 8
A8  - J4 9
A9  - J4 10
A10 - J4 13
A11 - J4 14
A12 - J4 15
A13 - J4 16
A14 - J4 17
A15 - J4 18 - POD 2 / 18

DATA

D0 - J3 45 - POD 1 / 0
D1 - J3 46
D2 - J3 47
D3 - J3 48
D4 - J3 49
D5 - J3 50
D6 - J3 51
D7 - J3 52 .. POD 1 / 7


LWR - J3 53   .. POD 1 / 8  [STAT.0]
LIORG - J3 54          [STAT.1]
LRFSH - J3 55          [STAT.2]
LMI   - J3 56         [STAT.3]
LBUSRQ- J3 57         [BUSREQ]*DISABLED
LNMI  - J3 58         [NMI]*DISABLED
LHALT - J3 59         [HALT]*DISABLED
LINT  - J3 60 - POD 1 / 15   [INT]*DISABLED

LMREQ - CLK0/J3 23  -- POD 1 J CLK  ( Memory Request )
LIORQ  - CLK1/J3 21   -- POD 2 K CLK ( IO Request )
LRFSH  - CLK2/J3 17   -- POD 3 L CLK ( Refresh )

LBUSAK - J3 19       -- POD 3 / 0 ( BUS Ack ) ** not in .text file.

LWAIT  - WT5 -- NC ( if you wanted to see this, you need to run a jumper from WT5 over to WT3 or WT2 )

gslick:
HP 10300B Zilog Z80 Preprocessor for the HP 1650A/51A and HP 16510A Logic Analyzers
Operating Manual, Part Number 10300-90911, February 1989

Table 2-1 Z80 Signal List

CPU Signal  CPU Pin Label       Pod Bit
-----------+-------+-----------+---+-----
LMREQ       19      (Clock)     1   J CLK
LIORQ       20      (Clock)     2   K CLK
LRFSH       28      (Clock)     3   L CLK

A0          30      ADDR        2    0
A1          31      ADDR        2    1
A2          32      ADDR        2    2
A3          33      ADDR        2    3
A4          34      ADDR        2    4
A5          35      ADDR        2    5
A6          36      ADDR        2    6
A7          37      ADDR        2    7
A8          38      ADDR        2    8
A9          39      ADDR        2    9
A10         40      ADDR        2   10
A11          1      ADDR        2   11
A12          2      ADDR        2   12
A13          3      ADDR        2   13
A14          4      ADDR        2   14
A15          5      ADDR        2   15

D0          14      DATA        1    0
D1          15      DATA        1    1
D2          12      DATA        1    2
D3           8      DATA        1    3
D4           7      DATA        1    4
D5           9      DATA        1    5
D6          10      DATA        1    6
D7          13      DATA        1    7

LWR         22      STAT        1    8
LIORQ       20      STAT        1    9
LRFSH       28      STAT        1   10
LM1         27      STAT        1   11
LBUSREQ     25      (Note 1)    1   12
LNMI        17      (Note 1)    1   13
LHALT       18      (Note 1)    1   14
LINT        16      (Note 1)    1   15

Note 1: These signals are not required for inverse assembly and do not appear on the STAT label. However, they may be useful for Z80 analysis.

Clock on (Falling Edge of Clock J + Falling Edge of Clock K)
LMREQ is inverted by the interface module for Clock J
LIORQ is inverted by the interface module for Clock K

To filter out Z80 refresh cycles:
Clock on (Falling Edge of Clock J + Falling Edge of Clock K) * Clock L
Capture data on the falling edge of the J or K clock only when the L clock (LFRSH) is high (not a refresh cycle).

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