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HP Logic Analyzer Inverse Assemblers

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Hamster:
I would like two hours of my time cross refencing the docs you posted above and not the doc i can't seem to find...

Where did you find this document? And is there a scan available long with ones for the other IA Modules?

HP 10300B Zilog Z80 Preprocessor for the HP 1650A/51A and HP 16510A Logic Analyzers
Operating Manual, Part Number 10300-90911, February 1989

no amount of googling seems to be able to find said document.

MarkL:
I spent a little time to adapt gslick's IZ80_I.S (the disassembled IZ80_I.R) so that /WR was interpreted normally (i.e., not inverted as it appears from the preprocessor).  This allows it to be used with general purpose probing.  I called it mz80_p.  Zip archive below with the source and the .R file as assembled by the HP 10391B development package.

I also found that the multiple 240/241 buffers in the preprocessor must have delays that are significant to the state clocking.  When using the rising edge of /MREQ and /IOREQ as the clock directly from the CPU, the address and other lines can start changing before those rising edges.  This interferes with a valid capture of state data.  Changes in the address, data, and other lines are actually initiated inside the CPU by the rising edge of Phi (the Z80 clock input).

To keep with the goal of using only general purpose probes and not adding gates to implement delays, Master/Slave clocking was activated which clocks all state data into the slave latches on the rising edge of Phi.  Then on the rising edge of the master clock, /MREQ or /IOREQ, the analyzer completes the state capture.  This seems to work reliably.

User gslick presented a way to filter out refresh cycles in the listing by using the /RFSH signal as a clock qualifier.  An alternative way is to use the Conditional Store feature, and only store those states which are not refreshes.  The end result is the same, but this way preserves a clock input for possibly something else.

Screen captures of various settings I used and output examples below.  I've probed all pins except power, but obviously this is not necessary.  Eventually I'll probably make an adapter to make this easier to set up.

I used mz80_p.r on a 16702B with a 16752A card, which needs to be imported by the IAL utility first.

Please post success or any problems with mz80_p if you try it.

EDIT:  Oops, forgot the zip file and fix typo....

gslick:
At the same time you were doing that, I was working on the X86 DLL General Purpose Probe version for the 1680/1690/16800/16900 series.

One thing I did different was to set the Slave Clock to be both edges of the Z80 CPU clock. If I understand the Z80 timing diagrams correctly, opcode fetch and interrupt ack cycles end just after a rising edge of the Z80 CPU clock, while memory and I/O read and write cycles end just after a falling edge of the Z80 CPU clock

CPU Signal  CPU Pin Label       Pod Bit
-----------+-------+-----------+---+-----
CLK          6      CLK-J       1   J CLK
LMREQ       19      LMREQ-K     2   K CLK
LIORQ       20      LIORQ-L     3   L CLK
LRFSH       28      LRFSH-M     4   M CLK

A0          30      ADDR        2    0
A1          31      ADDR        2    1
A2          32      ADDR        2    2
A3          33      ADDR        2    3
A4          34      ADDR        2    4
A5          35      ADDR        2    5
A6          36      ADDR        2    6
A7          37      ADDR        2    7
A8          38      ADDR        2    8
A9          39      ADDR        2    9
A10         40      ADDR        2   10
A11          1      ADDR        2   11
A12          2      ADDR        2   12
A13          3      ADDR        2   13
A14          4      ADDR        2   14
A15          5      ADDR        2   15

D0          14      DATA        1    0
D1          15      DATA        1    1
D2          12      DATA        1    2
D3           8      DATA        1    3
D4           7      DATA        1    4
D5           9      DATA        1    5
D6          10      DATA        1    6
D7          13      DATA        1    7

LWR         22      STAT        1    8
LIORQ       20      STAT        1    9
LRFSH       28      STAT        1   10
LM1         27      STAT        1   11
LBUSREQ     25      (Note 1)    1   12
LNMI        17      (Note 1)    1   13
LHALT       18      (Note 1)    1   14
LINT        16      (Note 1)    1   15

Note 1: These signals are not required for inverse assembly and do not appear on the STAT label. However, they may be useful for Z80 analysis.

Slave Clock:
Both Edges of Clock J

Master Clock:
(Rising Edge of Clock K + Rising Edge of Clock L)
Filter Out Refresh Cycles:
(Rising Edge of Clock K + Rising Edge of Clock L) * Clock M

gslick:
What do you call those 1-to-4 0.1 pin header breakout connectors? I couldn't guess the correct search term to find them. Where can you get them? I could have used some of those to make it easier to attach the doubled up flying lead connections to the DIP test clip.

MarkL:

--- Quote from: gslick on March 18, 2024, 01:29:06 am ---What do you call those 1-to-4 0.1 pin header breakout connectors? I couldn't guess the correct search term to find them. Where can you get them? I could have used some of those to make it easier to attach the doubled up flying lead connections to the DIP test clip.

--- End quote ---
The part number is HP 16515-27601 "GND CONNECTOR".  They're included with the 16517-68701 Master Board Accessory Kit and 16518-68701 Expander Board Accessory Kit., but only two per kit.  I haven't seen them anywhere else.  They're fairly handy and I'd buy a pile of them if I could find them in quantity.

I think you're right about the memory and I/O cycles.  It is a little different than the opcode fetch.  Using the rising edge of CLK cuts the sample window a little short, but it still seems to be sampled with plenty of margin.  Properly, though, I think you're right to sample on both edges.  I'll have to look a little more into this.

Did you try the IA I posted, or did you already have a version?  Just wanted to confirm it's working ok for others.  If you already modified the Z80 IA and posted it before, sorry I missed it.

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