Author Topic: HP Logic Analyzer Inverse Assemblers  (Read 9029 times)

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Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #50 on: May 07, 2020, 09:41:32 pm »
Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?
...
It sounds like you might have the "missing pullup resistor" problem, the same as the 167xx series:

  https://www.eevblog.com/forum/testgear/hp-16702a-mouse/msg374967/#msg374967

Sometimes non-Agilent keyboards and mice work, sometimes they don't.
Interesting - I have a bunch of cheap PS2 mice I purchased a while ago (like 10 for $10 or something silly) that were to be used on the analyser (well, one of them anyway!) but didnt work - hopefully this might fix it :) Will fire up the old girl at the weekend and try get it up and running - I'm very keen to get the 6502 setup working - I'll aim to make an adapter PCB to make it fast to set it up, else its too much of a hassle to connect all the probes. The adapter I linked to earlier seems to have the termination network (2 resistors and a capacitor) per signal but no logic - I guess something along the lines of the Z80 one would be a starting point but it would be nice to find someone who has one and replicate it.

Are the 40 pin pod connector pinouts fairly standard across the HP 16xx(x) range? Initial board will be for the HP 16xxx as that is what I have on hand.
« Last Edit: May 07, 2020, 09:44:13 pm by deanclaxton »
 

Online TK

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #51 on: May 07, 2020, 10:41:41 pm »
The 40-pin pod connector is fairly standard.  If you want to play with inverse assemblers, make sure to create the adapter following the configuration file pinout for the ADDR, DATA and STAT signals as defined in the inverse assembler configuration file.  Connecting the POD pins to a 6502 or Z80 is not that difficult, just 16 address lines, 8 data lines and around 4 stat lines including correct clock combinations.
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #52 on: May 08, 2020, 06:20:27 am »
The 40-pin pod connector is fairly standard.  If you want to play with inverse assemblers, make sure to create the adapter following the configuration file pinout for the ADDR, DATA and STAT signals as defined in the inverse assembler configuration file.  Connecting the POD pins to a 6502 or Z80 is not that difficult, just 16 address lines, 8 data lines and around 4 stat lines including correct clock combinations.

Will do. I have a 6502 IA here : https://www.dropbox.com/s/bjot0hxo9695s35/ia6502.zip?dl=0

Its not clear from the .S file which pod pins go where but it does list the input status bits and clocking on the falling edge of phi 2 :

************************************************************************
* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.
*

I'll have to read back through this thread to understand how to pull the required info from the other files.
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #53 on: May 08, 2020, 04:09:02 pm »
In 6502.S, the CASE_OF statement on line 101 says that it only cares about bits 4 through 1 of the STAT column.

So, the STAT column needs 5 signals assigned to it (MSB to LSB): R/W, RST, NMI, INT, and <anything>.  You can assign SYNC to bit 0 if you want.

The bit numbers shown in the beginning of 6502.S are probably just the assignments for those signals coming in from a probe pod.  You don't have to use those exact assignments, as long as the bits in your STAT column are defined in the order above.

That should work, but caveat that I don't have a 6502 to verify it.
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #54 on: May 08, 2020, 08:29:24 pm »
Ah ok. Do these files lock in particular pods and pod signals that it expects to be connected to data and address busses?

Ie pod 3, signal 0 = address 0?

I suppose this will all become clear once I get my unit up and running :)
« Last Edit: May 08, 2020, 08:44:36 pm by deanclaxton »
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #55 on: May 08, 2020, 10:13:52 pm »
The signal mapping is completely flexible.

Connect up the pods as you like.  But to keep things sane, you should probably assign one pod to the ADDR lines, and one pod to STAT and DATA signals.  Preserve the ordering of MSB to LSB for the data and address lines.

The physical to logical mapping for each incoming probe signal is done in the pod assignment tab.  The field (column) names ADDR, DATA, and STAT are significant to the IA.  The IA expects to find the address signals from A15 to A0 assigned to ADDR, D7 to D0 to DATA, and the control signals to STAT as previously noted.

If you haven't used one of these LAs before, take a stroll through the help when you get your system running.  It's context sensitive, and it's the main source of documentation for all HW and SW operations.

The help files are also available on keysight.com in PDF under the various 167xx product home pages, but they're a bit scattered.  You have to look at each product home pages to really find everything.
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #56 on: May 08, 2020, 11:33:25 pm »
Thanks Mark - thats excellent. I've got it up and running - turns out the previous owner had done a complete rebuild before passing it on. I found a mouse (MS Intellimouse 1.1A USB with PS2 adapter) and keyboard (IBM KB-0225 PS2 keyboard) that work and am currently using the VGA output. I believe all the optional licenses are installed already as well. It has some IA's installed as well so I loaded up a 68000 one to take a look. I can see the pod assignment and under the fomat tab it shows all the various mapping (lots of signals mapped in).

Question for now would be whether the 6502 signals would need any timing adjustment as per the Z80 example where each signal is buffered plus a few are slightly delayed via additional gates etc. I'll throw together an initial adapter board and give it a go. If the logic analyser is set to sample the data on the falling edge of the phi2 clock (in the case of the 6502 example), would a delay ensure that the signals are valid when the analyser samples them - ie is it possible that it would otherwise sample the signals before they are valid - by delaying the phi2 clock signal a few ns perhaps ensures the bus data is valid when sampled? I guess I need to look at the 6502 datasheet for that info, and to actually start playing around with it to work it all out. In general I wonder if cpu adapters sold by vendors would buffer all the bus signals (as per the Z80 one), and why that might be required.

EDIT : Ah - reading back in the thread here (https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485) it seems that the Z80 timing is more complex - seems that TK was using the 6502 inverse assembler directly, so perhaps I wont need anything on my adapter other than the termination. Will give it a go!

« Last Edit: May 09, 2020, 12:19:33 am by deanclaxton »
 

Online TK

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #57 on: May 09, 2020, 03:03:12 am »
It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #58 on: May 09, 2020, 03:23:03 am »
It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA

Thanks TK - is is possible to see your configuration as to which pod pins you used to interface to the 6502? Also did you use the IA from Phil Pemberton or another one?
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #59 on: May 10, 2020, 10:52:18 pm »
I said:
The signal mapping is completely flexible.

Connect up the pods as you like.  But to keep things sane, you should probably assign one pod to the ADDR lines, and one pod to STAT and DATA signals.  Preserve the ordering of MSB to LSB for the data and address lines.
...

It dawned on me today that you said you have a 16602A.  I don't have one to verify, but I don't believe arbitrary bit ordering is supported on it.  That feature seems to have been added in an early 2.xx release, and a recent post in the HPAK groups.io says that the 16600 series doesn't run version 2.xx.

So... What I said about ADDR, DATA, and STAT is still true, expect you DO have to connect the signals in the right physical order of MSB to LSB (consecutively) so that the logical bits are also in the same order when you define those labels.  A minor detail, but I didn't want to leave you with incorrect info, wondering what I was talking about.

On the setup and hold question, the spec sheet says that the 16602A has an adjustable setup and hold time of 0 to 4.5ns, if you run into trouble with delay.
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #60 on: May 11, 2020, 12:42:39 am »
It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA

Thanks TK - is is possible to see your configuration as to which pod pins you used to interface to the 6502? Also did you use the IA from Phil Pemberton or another one?

This is how I configured a 1670 series analyzer to use the 6502 inverse assembler:





 
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Offline philpem

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #61 on: May 12, 2020, 08:26:17 am »
Its not clear from the .S file which pod pins go where but it does list the input status bits and clocking on the falling edge of phi 2 :

************************************************************************
* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.
*

That's the inverse assembler I wrote back while I was in my late teens... I was building a 6502 SBC and wrote an IA to help debug it.

To get it working, you hook the CPU address bus up to one pod (16 bits) and declare it as ADDR in the IA. Hook the data bus up to the low half of the other probe and declare it as DATA. Hook up the STAT lines as above. The bits refer to the bit assignments in the STAT word -- from memory, I assigned the whole top byte to STAT then declared separate labels for the individual pins.

Connect PHI2-Out from the 6502 to the J-clock or K-clock. Set that as your storage clock, triggered on a H->L edge.

The IA's written for the Western Design Center W65C02S, so it supports the extended instructions (at least the ones supported by that particular chip).

There was never a test adapter. I shoved a DIN41612 connector into the backplane and wired up pods to the back of it. These days if I was planning to use the rig more than once, I'd use the 20way IDC, Samtec or Mictor transition adapters and spin a PCB...

Glad to see this crusty old code is still useful nearly 20 years later! Shame I forgot to stick my name on it, though I didn't expect it to spread far!
It came with a version of IALDOWN I wrote in Borland Delphi because the DOS one didn't work under Windows.

My notes on IAL are probably still floating around, I ripped apart the IAL .R format and instruction set during a break at university.

Cheers,
Phil.
Phil / M0OFX -- Electronics/Software Engineer
"Why do I have a room full of test gear? Why, it saves on the heating bill!"
 
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Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #62 on: May 12, 2020, 10:29:33 am »
Wow - thats awesome - thanks Phil! I'm going to lay out a PCB for this - probably with a jumper to select which clock (phi0, 1, or 2) wires to the pod, and also include a couple of clip points for +5V and GND which would give me a handy location to safely connect a logic probe, scope ground lead, etc (for additional troubleshooting on a board).

There are a few leftover pod signal lines that could pick up the remaining signals on a 6502 (SO, RDY) for timing analysis/general troubleshooting, however the 65C02 has a few more again (MLB, BE, VPB). VPB (pin 1) is another GND on a 6502. Rather than use another pod connector, I might have to decide which of these signals are must - haves. Will check out some of the boards I'd be troubleshooting to determine which were used commonly.
« Last Edit: May 12, 2020, 10:49:02 am by deanclaxton »
 

Offline xadhoom76

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #63 on: June 02, 2020, 07:20:47 pm »
hi to all and thanks for this epic thread !
I'm new owner of HP 16500A, I have timing/state modules the one with ID 31
When I try to load any invasm ( would like to use it for z80 ) i got SOFTWARE ERROR - Please record these number  0010 0000006E 2000
My unit is with 1MB ram and Operating System v.6.
Thanks
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #64 on: June 02, 2020, 11:48:38 pm »
hi to all and thanks for this epic thread !
I'm new owner of HP 16500A, I have timing/state modules the one with ID 31
When I try to load any invasm ( would like to use it for z80 ) i got SOFTWARE ERROR - Please record these number  0010 0000006E 2000
My unit is with 1MB ram and Operating System v.6.
Thanks

I just tried loading some of the INVASM files on a 16510A analyzer module installed in a 16500A mainframe with a 1MB CPU running Version 6.00 of the system software and they seemed to load fine for me without any error.

Maybe something went wrong with the method you used to create the floppy disks you are using. Do you have a PC with a 3.5-inch floppy drive that you can use to boot into real mode MS-DOS? If you can download and run ImageDisk 1.18 on a PC in real mode MS-DOS I have attached an ImageDisk image of a 720-KB LIF format floppy disk (not a 1.44MB HD floppy disk) that contains the 16500A Version 6.00 SYSTEM_ and SYSTEM_031 files plus some Config and IA files that I was able to load without errors.

ImageDisk 1.18 download link here:
http://www.classiccmp.org/dunfield/img/index.htm

Code: [Select]
DISK DIRECTORY                                                                 

DOS Filename  Date    Time     Bytes   Description
____________  _______ ________ _______ ________________________________

C68000_P       2Jun20 13:05:19   18944 68000 CONFIG FOR GP PROBES   1_0
C68008_P       2Jun20 13:05:50   18944 68008 CONFIG FOR GP PROBES   1_0
C6800_P        2Jun20 13:06:11   18432 6800/02 CONFIG FOR GP PROBES 1_0
C68010_P       2Jun20 13:06:32   18944 68010 CONFIG FOR GP PROBES   1_0
C6809E_P       2Jun20 13:06:52   18432 6809E CONFIG FOR GP PROBES   1_0
C6809_P        2Jun20 13:07:08   18432 6809 CONFIG FOR GP PROBES    1_0
C8085_P        2Jun20 13:07:29   18432 8085 CONFIG FOR GP PROBES    1_0
I68000_P       2Jun20 13:07:50    9216 68000 IA FOR GP PROBES       1_0
I68008_P       2Jun20 13:08:05    9728 68008 IA FOR GP PROBES       1_0
I6800_P        2Jun20 13:08:21    9216 6800/02 IA FOR GP PROBES     1_0
I68010_P       2Jun20 13:08:37    9984 68010 IA FOR GP PROBES       1_0
I6809E_P       2Jun20 13:08:54   10240 6809E IA FOR GP PROBES       1_0
I6809_P        2Jun20 13:09:09   10240 6809 IA FOR GP PROBES        1_0
I8085_IP       2Jun20 13:09:39    5120 8085 INVERSE ASSEMBLER       1_0
SYSTEM_       31Oct89  0:02:00  233728 HP16500A System Software  V06.00
SYSTEM_031    31Oct89  0:02:00  252160 35MHz State/100MHz Timing V06.00

 
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Offline xadhoom76

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #65 on: June 03, 2020, 08:42:00 am »
Great it WORKS !!! Thanks Master !
 

Offline xadhoom76

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #66 on: June 04, 2020, 06:16:15 am »
In my test I use lifutil but the files listed on HP16500A seems to miss some
Your listing
DISK DIRECTORY                                                                 

DOS Filename  Date    Time     Bytes   Description
____________  _______ ________ _______ ________________________________

C68000_P       2Jun20 13:05:19   18944 68000 CONFIG FOR GP PROBES   1_0
C68008_P       2Jun20 13:05:50   18944 68008 CONFIG FOR GP PROBES   1_0
C6800_P        2Jun20 13:06:11   18432 6800/02 CONFIG FOR GP PROBES 1_0
C68010_P       2Jun20 13:06:32   18944 68010 CONFIG FOR GP PROBES   1_0
C6809E_P       2Jun20 13:06:52   18432 6809E CONFIG FOR GP PROBES   1_0
C6809_P        2Jun20 13:07:08   18432 6809 CONFIG FOR GP PROBES    1_0
C8085_P        2Jun20 13:07:29   18432 8085 CONFIG FOR GP PROBES    1_0
I68000_P       2Jun20 13:07:50    9216 68000 IA FOR GP PROBES       1_0
I68008_P       2Jun20 13:08:05    9728 68008 IA FOR GP PROBES       1_0
I6800_P        2Jun20 13:08:21    9216 6800/02 IA FOR GP PROBES     1_0
I68010_P       2Jun20 13:08:37    9984 68010 IA FOR GP PROBES       1_0

If I add cz80_P and iz80_i it doesn't work and i notice the file is missing the description.

My add using lifutil could be wrong ?
I work in dos directly booting from a floppy on my old pc. then lifutil and I choos dos to lif .
I try different format of files ( DFS or other ) but no way to make it working.
Sorry to bored you but really do not understand why.
I would like to use 16500A with z80 and 6502
Best regards and thanks. I will try again , your floppy works great.
 


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