dc19 : b701d0 staa CmdTableIndex
dc1c : 86ee ldaa #$EE
dc1e : b101d0 cmpa CmdTableIndex
dc21 : 2609 bne LDFAA ; branch if valid CmdChar
dc23 : bdd6c0 jsr subResetCmdFlags
dc26 : 7ee3a0 jmp LE768 ; set flagCmdParse bit6 and rts
[SOURCE LINES]
File: test.lst
...
9029 dc19
9030 dc1c
9031 dc1e
9032 dc21
9033 dc23
9034 dc26
...
Been looking for an inverse assembler for the MC6800. Haven't found one yet, but thought it might be worthwhile to summarize what is available.
...I looked at IALDOWN a while ago hoping it would provide transformation clues for the 1631D:
If you don't have a .R file, or the .S source to build the .R file, I don't know if there is a way to use any of these old IAL style inverse assembler files with the 16900 series logic analyzer software. The files as they are normally distributed are after the IALDOWN tool has done some sort of undocumented transformation of the .R files. Maybe that transformation could be reverse engineered so that a tool could be written to do an inverse transformation back in .R files. Or maybe even disassemble the files back into functionally equivalent .S source files.
...
For example, I have a 16702B with a 16752A card and I've been successful using it on a 6802 processor. I can successfully load i6800_p, the inverse assembler for general purpose (flying lead) probes.
/* definitions for the different unique bit patterns for each instruction
* in the different instruction groups -- used by the interpreter
*/
/* instruction group 1 */
const u_int16 IF_OP = 4;
const u_int16 IF_BITS = 5;
const u_int16 ICASE_OP = 6;
const u_int16 ICASE_BITS = 7;
/* instruction group 2 */
const u_int16 IGO_TO = 4;
const u_int16 ICALL = 5;
const u_int16 ISTR_OUTPUT = 6;
const u_int16 INUM_OUTPUT = 7;
/* instruction group 3 */
const u_int16 ILOAD_ACC = 8;
const u_int16 IADD_ACC = 9;
const u_int16 ISUB_ACC = 10;
const u_int16 IAND_ACC = 11;
const u_int16 IOR_ACC = 12;
const u_int16 IXOR_ACC = 13;
const u_int16 ITAG_WITH = 14;
const u_int16 INP_ABS = 15;
/* instruction group 4 */
const u_int16 ISTORE_MEM = 4;
const u_int16 INC_MEM = 5;
const u_int16 IDEC_MEM = 6;
const u_int16 INP_ABSQ = 7;
/* instruction group 5 */
const u_int16 INP_REL = 2;
const u_int16 INP_RELQ = 3;
/* instruction group 6 */
const u_int16 IROT_LEFT = 8;
const u_int16 IROT_RIGHT = 9;
const u_int16 IEXT_BIT = 10;
const u_int16 IPOS_ABS = 11;
const u_int16 IPOS_REL = 12;
/* instruction group 7 */
const u_int16 INOP = 16;
const u_int16 ICOMP_ACC = 17;
const u_int16 ITWOCOMP_ACC = 18;
const u_int16 IRETURN = 19;
const u_int16 ION_TRACE = 20;
const u_int16 IOFF_TRACE = 21;
const u_int16 IABORT = 22;
const u_int16 IFNOT_MAP = 23;
const u_int16 IMARKLINE_O_NA = 24;
const u_int16 IMARKLINE_S_NA = 25;
const u_int16 IMARKLINE_O_A = 26;
const u_int16 IMARKLINE_S_A = 27;
const u_int16 IMARKSTATE_DISP = 28;
const u_int16 IMARKSTATE_SUP = 29;
const u_int16 INEWLINE = 30;
const u_int16 IFETCH_POSITION = 31;
/* instruction group 1 */
/* conditional instruction -- bit 15 is set */
/* instruction = (opcode >> 13) */
100x xxxx xxxx xxxx IF_OP = 4
101x xxxx xxxx xxxx IF_BITS = 5
110x xxxx xxxx xxxx ICASE_OP = 6
111x xxxx xxxx xxxx ICASE_BITS = 7
/* instruction group 2 */
/* transfer/output instruction -- bit 14 is set */
/* instruction = (opcode >> 12) */
0100 xxxx xxxx xxxx IGO_TO = 4
0101 xxxx xxxx xxxx ICALL = 5
0110 xxxx xxxx xxxx ISTR_OUTPUT = 6
0111 xxxx xxxx xxxx INUM_OUTPUT = 7
/* set immediate instruction -- bit 13 is on */
001x xxxx xxxx xxxx
/* instruction group 3 */
/* math instruction -- bit 12 is on */
/* instruction = (opcode >> 9) */
0001 000x xxxx xxxx ILOAD_ACC = 8
0001 001x xxxx xxxx IADD_ACC = 9
0001 010x xxxx xxxx ISUB_ACC = 10
0001 011x xxxx xxxx IAND_ACC = 11
0001 100x xxxx xxxx IOR_ACC = 12
0001 101x xxxx xxxx IXOR_ACC = 13
0001 110x xxxx xxxx ITAG_WITH = 14
0001 111x xxxx xxxx INP_ABS = 15
/* instruction group 4 */
/* single variable instruction -- bit 11 is on */
/* instruction = (opcode >> 9) */
0000 100x xxxx xxxx ISTORE_MEM = 4
0000 101x xxxx xxxx INC_MEM = 5
0000 110x xxxx xxxx IDEC_MEM = 6
0000 111x xxxx xxxx INP_ABSQ = 7
/* instruction group 5 */
/* input relative instruction -- bit 10 is on */
/* instruction = (opcode >> 9) */
0000 010x xxxx xxxx INP_REL = 2
0000 011x xxxx xxxx INP_RELQ = 3
/* instruction group 6 */
/* single operand instruction -- bit 9 is on */
/* instruction = (opcode >> 6) */
0000 0010 00xx xxxx IROT_LEFT = 8
0000 0010 01xx xxxx IROT_RIGHT = 9
0000 0010 10xx xxxx IEXT_BIT = 10
0000 0010 11xx xxxx IPOS_ABS = 11
0000 0011 00xx xxxx IPOS_REL = 12
/* instruction group 7 */
/* implied operand instruction - bits 15-5 off, bit 4 on */
0000 0000 0001 0000 INOP = 16
0000 0000 0001 0001 ICOMP_ACC = 17
0000 0000 0001 0010 ITWOCOMP_ACC = 18
0000 0000 0001 0011 IRETURN = 19
0000 0000 0001 0100 ION_TRACE = 20
0000 0000 0001 0101 IOFF_TRACE = 21
0000 0000 0001 0110 IABORT = 22
0000 0000 0001 0111 IFNOT_MAP = 23
0000 0000 0001 1000 IMARKLINE_O_NA = 24
0000 0000 0001 1001 IMARKLINE_S_NA = 25
0000 0000 0001 1010 IMARKLINE_O_A = 26
0000 0000 0001 1011 IMARKLINE_S_A = 27
0000 0000 0001 1100 IMARKSTATE_DISP = 28
0000 0000 0001 1101 IMARKSTATE_SUP = 29
0000 0000 0001 1110 INEWLINE = 30
0000 0000 0001 1111 IFETCH_POSITION = 31
I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.I think we're starting to find enough pieces.
IA File: i68000_i
IA Description: "68000 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: i68000_p
IA Description: "68000 IA FOR GP PROBES 1_0"
IA Field Option: B
IA File: i68008_i
IA Description: "68008 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: i68008_p
IA Description: "68008 IA FOR GP PROBES 1_0"
IA Field Option: B
IA File: i6800_i
IA Description: "6800/02 IA FOR INTERFACE 1_0"
IA Field Option: A
IA File: i6800_p
IA Description: "6800/02 IA FOR GP PROBES 1_0"
IA Field Option: B
IA File: i68010_i
IA Description: "68010 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: i68010_p
IA Description: "68010 IA FOR GP PROBES 1_0"
IA Field Option: B
IA File: i68020_i.p
IA Description: "68020 INVERSE ASSEMBLER 1_0"
IA Field Option: C
IA File: i6809e_p
IA Description: "6809E IA FOR GP PROBES 1_0"
IA Field Option: B
IA File: i6809_i
IA Description: "6809/9E IA FOR INTERFACE 1_0"
IA Field Option: A
IA File: i6809_p
IA Description: "6809 IA FOR GP PROBES 1_0"
IA Field Option: B
IA File: i80186e_.i
IA Description: "80186 ENHANCED IA 1_0"
IA Field Option: B
IA File: i80186_i
IA Description: "80186 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: i80188e_.i
IA Description: "80188 ENHANCED IA 1_0"
IA Field Option: B
IA File: i80188_i
IA Description: "80188 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: i80286_i
IA Description: "80286 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: i80386_8.7
IA Description: "80386 IA WITH 80X87 1_0"
IA Field Option: D
IA File: i80386_i
IA Description: "80386 IA FOR INTERFACE 1_0"
IA Field Option: D
IA File: i8085_ip
IA Description: "8085 INVERSE ASSEMBLER 1_0"
IA Field Option: A
IA File: i8086_i
IA Description: "8086 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: i8088_i
IA Description: "8088 IA FOR INTERFACE 1_0"
IA Field Option: B
IA File: insc800_.i
IA Description: "NSC800 IA FOR INTERFACE 1_0"
IA Field Option: A
IA File: iz80_i
IA Description: "Z80 IA FOR INTERFACE 1_0"
IA Field Option: A
I finished up the .R extractor and ran it on all the files in invasm.zip. Attached is invasm_v3.zip which has the results as well as the previous output from configtxt.
Title: 8085 CONFIG FOR INTERFACE 1_0
Pod assigments (? = disabled)
-----------------------------
Label 0: ADDR (16 bits): A2: ******** ********
Label 1: DATA ( 8 bits): A1: ........ ********
Label 2: STAT ( 4 bits): A1: ....**** ........
...I looked at this with your posting and the user manual in hand. Unfortunately, it's not immediately obvious where the clocking information lies or how it's encoded in the configuration file.
For the configuration text, have you looked at trying to decode the Master and Slave clock specifications, and the Normal, Demultiplex, or Mixed Clocks modes for each pod?
...
LABEL_0015
GOTO LABEL_0016
LABEL_0015
GOTO LABEL_0026
"IAL"
IF TASK = 3 THEN GOTO LABEL_0010
IF TASK = 4 THEN GOTO LABEL_0015
IF TASK = 5 THEN GOTO LABEL_0015
OUTPUT "Illegal Task Request"
ABORT
OUTPUT "Data Error"
ABORT
LABEL_000D
POSITION ABS,1
OUTPUT "Illegal Opcode"
ABORT
LABEL_0010
LOAD ID_CODE
IF 7,0 = VAR_0048 THEN GOTO LABEL_0016
GOTO LABEL_0026
LABEL_0015
GOTO LABEL_0016
LABEL_0016
LOAD INPUT_TAG
IF 17,16 = 0 THEN GOTO LABEL_0043
LOAD INPUT_STATUS
IF 2,2 = 1 THEN GOTO LABEL_0043
LOAD INPUT_TAG
CASE_OF 1,0
GOTO LABEL_01A2
GOTO LABEL_0043
GOTO LABEL_0054
NOP
CASE_END
RETURN
LABEL_0026
LOAD INPUT_STATUS
IF 3,0 = 9 THEN GOTO LABEL_005B
LOAD INPUT_DATA
POSITION ABS,3
OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
POSITION REL,1
LOAD INPUT_STATUS
CASE_OF 3,0
OUTPUT "Illegal Opcode"
OUTPUT "operand fetch"
OUTPUT "stack read"
OUTPUT "stack write"
OUTPUT "stack read"
OUTPUT "stack write"
OUTPUT "halt"
OUTPUT "vector"
OUTPUT "unused"
OUTPUT "opcode fetch"
OUTPUT "DMA read"
OUTPUT "DMA write"
OUTPUT "memory write"
OUTPUT "memory read"
OUTPUT "out of synch"
OUTPUT "interrupt ack"
CASE_END
SET RETURN_FLAGS,0
RETURN
LABEL_0043
LOAD INPUT_DATA
POSITION ABS,3
OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
POSITION REL,1
LOAD INPUT_STATUS
CASE_OF 2,0
OUTPUT "non valid cycle"
OUTPUT "non valid cycle"
OUTPUT "memory write"
OUTPUT "memory read"
OUTPUT "dma or halt"
OUTPUT "dma or halt"
OUTPUT "dma or halt"
OUTPUT "dma or halt"
CASE_END
SET RETURN_FLAGS,0
RETURN
LABEL_0054
LOAD INPUT_DATA
POSITION ABS,3
OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
POSITION REL,1
OUTPUT "unused cycle"
SET RETURN_FLAGS,0
RETURN
LABEL_005B
SET RETURN_FLAGS,1
INPUT REL,0
LOAD INITIAL_DATA
CASE_OF 7,7
GOTO LABEL_0062
GOTO LABEL_0103
CASE_END
LABEL_0062
CASE_OF 7,4
GOTO LABEL_006C
GOTO LABEL_008C
GOTO LABEL_009F
GOTO LABEL_00C4
GOTO LABEL_00E2
GOTO LABEL_00E2
GOTO LABEL_00E2
GOTO LABEL_00E2
CASE_END
LABEL_006C
CASE_OF 3,0
GOTO LABEL_000D
OUTPUT "NOP"
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "TAP"
OUTPUT "TPA"
OUTPUT "INX"
OUTPUT "DEX"
GOTO LABEL_007F
GOTO LABEL_0081
GOTO LABEL_007F
GOTO LABEL_0081
GOTO LABEL_007F
GOTO LABEL_0081
CASE_END
RETURN
LABEL_007F
OUTPUT "CL"
GOTO LABEL_0082
LABEL_0081
OUTPUT "SE"
LABEL_0082
IF 2,1 = 1 THEN OUTPUT "V"
IF 2,1 = 2 THEN OUTPUT "C"
IF 2,1 = 3 THEN OUTPUT "I"
RETURN
LABEL_008C
CASE_OF 3,0
OUTPUT "SBA"
OUTPUT "CBA"
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "TAB"
OUTPUT "TBA"
GOTO LABEL_000D
OUTPUT "DAA"
GOTO LABEL_000D
OUTPUT "ABA"
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
CASE_END
RETURN
LABEL_009F
OUTPUT "B"
CASE_OF 3,0
OUTPUT "RA"
GOTO LABEL_000D
OUTPUT "HI"
OUTPUT "LS"
OUTPUT "CC"
OUTPUT "CS"
OUTPUT "NE"
OUTPUT "EQ"
OUTPUT "VC"
OUTPUT "VS"
OUTPUT "PL"
OUTPUT "MI"
OUTPUT "GE"
OUTPUT "LT"
OUTPUT "GT"
OUTPUT "LE"
CASE_END
LABEL_00B2
INCREMENT INPUT_ADDRESS
LOAD INPUT_ADDRESS
ADD 1
STORE VAR_003E
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
LOAD INPUT_DATA
POSITION ABS,6
IF 7,7 = 1 THEN INCLUSIVE_OR VAR_0046
ADD VAR_003E
AND VAR_0042
IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
RETURN
LABEL_00C4
CASE_OF 3,0
OUTPUT "TSX"
OUTPUT "INS"
GOTO LABEL_00D7
GOTO LABEL_00D7
OUTPUT "DES"
OUTPUT "TXS"
GOTO LABEL_00D7
GOTO LABEL_00D7
GOTO LABEL_000D
OUTPUT "RTS"
GOTO LABEL_000D
OUTPUT "RTI"
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "WAI"
OUTPUT "SWI"
CASE_END
RETURN
LABEL_00D7
IF 2,2 = 0 THEN OUTPUT "PUL"
IF 2,2 = 1 THEN OUTPUT "PSH"
CASE_OF 0,0
GOTO LABEL_00FF
GOTO LABEL_0101
CASE_END
RETURN
LABEL_00E2
CASE_OF 3,0
OUTPUT "NEG"
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "COM"
OUTPUT "LSR"
GOTO LABEL_000D
OUTPUT "ROR"
OUTPUT "ASR"
OUTPUT "ASL"
OUTPUT "ROL"
OUTPUT "DEC"
GOTO LABEL_000D
OUTPUT "INC"
OUTPUT "TST"
GOTO LABEL_00F5
OUTPUT "CLR"
CASE_END
GOTO LABEL_00F9
LABEL_00F5
CASE_OF 5,5
GOTO LABEL_000D
OUTPUT "JMP"
CASE_END
LABEL_00F9
CASE_OF 5,4
GOTO LABEL_00FF
GOTO LABEL_0101
GOTO LABEL_016B
GOTO LABEL_0170
CASE_END
LABEL_00FF
OUTPUT "A"
RETURN
LABEL_0101
OUTPUT "B"
RETURN
LABEL_0103
CASE_OF 3,0
OUTPUT "SUB"
OUTPUT "CMP"
OUTPUT "SBC"
GOTO LABEL_000D
OUTPUT "AND"
OUTPUT "BIT"
OUTPUT "LDA"
GOTO LABEL_0116
OUTPUT "EOR"
OUTPUT "ADC"
OUTPUT "ORA"
OUTPUT "ADD"
GOTO LABEL_011E
GOTO LABEL_0126
GOTO LABEL_0138
GOTO LABEL_0141
CASE_END
GOTO LABEL_0150
LABEL_0116
IF 7,4 = 8 THEN GOTO LABEL_000D
IF 7,4 = 12 THEN GOTO LABEL_000D
OUTPUT "STA"
GOTO LABEL_0150
LABEL_011E
IF 7,4 >= 12 THEN GOTO LABEL_000D
OUTPUT "CPX"
IF 5,4 = 0 THEN GOTO LABEL_0161
GOTO LABEL_0156
LABEL_0126
IF 7,4 = 9 THEN GOTO LABEL_000D
IF 7,4 >= 12 THEN GOTO LABEL_000D
IF 5,4 = 0 THEN GOTO LABEL_0136
OUTPUT "JSR"
IF 5,4 = 2 THEN GOTO LABEL_016B
IF 5,4 = 3 THEN GOTO LABEL_0170
LABEL_0136
OUTPUT "BSR"
GOTO LABEL_00B2
LABEL_0138
OUTPUT "LD"
CASE_OF 6,6
OUTPUT "S"
OUTPUT "X"
CASE_END
IF 5,4 = 0 THEN GOTO LABEL_0161
GOTO LABEL_0156
LABEL_0141
IF 7,4 = 8 THEN GOTO LABEL_000D
IF 7,4 = 12 THEN GOTO LABEL_000D
OUTPUT "ST"
CASE_OF 6,6
OUTPUT "S"
OUTPUT "X"
CASE_END
IF 5,4 = 0 THEN GOTO LABEL_0161
GOTO LABEL_0156
LABEL_0150
IF 6,6 = 0 THEN CALL LABEL_00FF
IF 6,6 = 1 THEN CALL LABEL_0101
LABEL_0156
CASE_OF 5,4
GOTO LABEL_015C
GOTO LABEL_0166
GOTO LABEL_016B
GOTO LABEL_0170
CASE_END
LABEL_015C
POSITION ABS,6
OUTPUT "#"
CALL LABEL_0175
OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
RETURN
LABEL_0161
POSITION ABS,6
OUTPUT "#"
CALL LABEL_017E
OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
RETURN
LABEL_0166
POSITION ABS,6
CALL LABEL_0175
IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
RETURN
LABEL_016B
POSITION ABS,6
CALL LABEL_0175
OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
OUTPUT ",X"
RETURN
LABEL_0170
POSITION ABS,6
CALL LABEL_017E
IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
RETURN
LABEL_0175
INCREMENT INPUT_ADDRESS
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
LOAD INPUT_DATA
RETURN
LABEL_017C
OUTPUT "**"
ABORT
LABEL_017E
INCREMENT INPUT_ADDRESS
LOAD INPUT_ADDRESS
STORE VAR_003C
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_0192
LOAD INPUT_DATA
ROTATE LEFT,8
AND VAR_0044
STORE VAR_0034
INCREMENT INPUT_ADDRESS
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_019D
LOAD INPUT_DATA
AND VAR_004A
INCLUSIVE_OR VAR_0034
RETURN
LABEL_0192
OUTPUT "**"
LOAD VAR_003C
STORE INPUT_ADDRESS
INCREMENT INPUT_ADDRESS
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_01A0
LOAD INPUT_DATA
OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
ABORT
LABEL_019D
LOAD VAR_0034
ROTATE RIGHT,8
OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
LABEL_01A0
OUTPUT "**"
ABORT
LABEL_01A2
SET VAR_0040,0
LABEL_01A3
LOAD INPUT_STATUS
IF 1,0 = 3 THEN GOTO LABEL_01AE
TAG_WITH 2
INCREMENT VAR_0040
INPUT REL,VAR_0040
IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
GOTO LABEL_01A3
LABEL_01AE
LOAD INPUT_DATA
CASE_OF 7,0
GOTO LABEL_000D
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
LOAD VAR_004C
LOAD VAR_004E
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
GOTO LABEL_000D
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_0050
GOTO LABEL_000D
LOAD VAR_0052
LOAD VAR_0054
LOAD VAR_0056
LOAD VAR_0058
LOAD VAR_005A
LOAD VAR_005C
LOAD VAR_005E
LOAD VAR_0060
LOAD VAR_0062
LOAD VAR_0064
LOAD VAR_0066
LOAD VAR_0068
LOAD VAR_006A
LOAD VAR_006C
LOAD VAR_006E
LOAD VAR_0070
LOAD VAR_0072
LOAD VAR_0074
LOAD VAR_0076
LOAD VAR_0078
LOAD VAR_007A
LOAD VAR_007C
GOTO LABEL_000D
LOAD VAR_007E
GOTO LABEL_000D
LOAD VAR_0080
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_0082
LOAD VAR_0084
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD VAR_0086
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_0088
LOAD VAR_008A
GOTO LABEL_000D
LOAD VAR_008C
LOAD VAR_008E
LOAD VAR_0090
LOAD VAR_0092
LOAD VAR_0094
GOTO LABEL_000D
LOAD VAR_0096
LOAD VAR_0098
LOAD VAR_009A
LOAD VAR_009C
LOAD VAR_009E
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_00A0
LOAD VAR_00A2
GOTO LABEL_000D
LOAD VAR_00A4
LOAD VAR_00A6
LOAD VAR_00A8
LOAD VAR_00AA
LOAD VAR_00AC
GOTO LABEL_000D
LOAD VAR_00AE
LOAD VAR_00B0
LOAD VAR_00B2
LOAD VAR_00B4
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
LOAD 52
LOAD VAR_00B6
LOAD VAR_00B8
LOAD VAR_00BA
GOTO LABEL_000D
LOAD VAR_00BC
LOAD VAR_00BE
LOAD VAR_00C0
GOTO LABEL_000D
LOAD VAR_00C2
LOAD VAR_00C4
LOAD VAR_00C6
LOAD VAR_00C8
LOAD VAR_00CA
LOAD VAR_00CC
LOAD VAR_00CE
LOAD VAR_00D0
LOAD VAR_00D2
GOTO LABEL_000D
LOAD VAR_00D4
LOAD VAR_00D6
LOAD VAR_00D8
LOAD VAR_00DA
LOAD VAR_00DC
GOTO LABEL_000D
LOAD VAR_00DE
LOAD VAR_00E0
LOAD VAR_00E2
LOAD VAR_00E4
LOAD VAR_00E6
LOAD VAR_00E8
LOAD VAR_00EA
LOAD VAR_00EC
LOAD VAR_00EE
LOAD VAR_00F0
LOAD VAR_00F2
LOAD VAR_00F4
LOAD VAR_00F6
LOAD VAR_00F8
LOAD VAR_00FA
GOTO LABEL_000D
LOAD VAR_00FC
LOAD VAR_00FE
LOAD VAR_0100
LOAD VAR_0102
LOAD VAR_0104
LOAD VAR_0106
LOAD VAR_0108
LOAD VAR_010A
LOAD VAR_010C
LOAD VAR_010E
LOAD VAR_0110
LOAD VAR_0112
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_0114
GOTO LABEL_000D
LOAD VAR_0116
LOAD VAR_0118
LOAD VAR_011A
GOTO LABEL_000D
LOAD VAR_011C
LOAD VAR_011E
LOAD VAR_0120
LOAD VAR_0122
LOAD VAR_0124
LOAD VAR_0126
LOAD VAR_0128
LOAD VAR_012A
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_012C
LOAD VAR_012E
LOAD VAR_0130
LOAD VAR_0132
LOAD VAR_0134
GOTO LABEL_000D
LOAD VAR_0136
LOAD VAR_0138
LOAD VAR_013A
LOAD VAR_013C
LOAD VAR_013E
LOAD VAR_0140
LOAD VAR_0142
LOAD VAR_0144
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_0146
LOAD VAR_0148
LOAD VAR_014A
LOAD VAR_014C
LOAD VAR_014E
GOTO LABEL_000D
LOAD VAR_0150
LOAD VAR_0152
LOAD VAR_0154
LOAD VAR_0156
LOAD VAR_0158
LOAD VAR_015A
LOAD VAR_015C
LOAD VAR_015E
GOTO LABEL_000D
GOTO LABEL_000D
LOAD VAR_0160
LOAD VAR_0162
CASE_END
LABEL_02B1
STORE VAR_0036
AND 3
STORE VAR_003A
IF 1,0 = 3 THEN GOTO LABEL_005B
TAG_WITH VAR_003A
LABEL_02B8
INCREMENT VAR_0040
INPUT REL,VAR_0040
IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
LOAD INPUT_STATUS
IF 2,2 = 1 THEN GOTO LABEL_02B8
LOAD VAR_0036
ROTATE RIGHT,2
GOTO LABEL_02B1
"IAL"
*
* Original Source File Name: d:\ial\procs\i6800_p.s
*
LABEL_TITLE " 6800/6802 Mnemonic"
BASE_TITLE " hex"
SEARCH_LIMIT 12
DEFAULT_WIDTH 21
MAPPED_WIDTH 21
VAR_0034 VARIABLE 000000000H
VAR_0036 VARIABLE 000000000H
VAR_0038 VARIABLE 000000000H * unreferenced
VAR_003A VARIABLE 000000000H
VAR_003C VARIABLE 000000000H
VAR_003E VARIABLE 000000000H
VAR_0040 VARIABLE 000000000H
FMT_0010 FORMAT 16,HEX,4
FMT_0012 FORMAT 8,HEX,2
STR_0014 ASCII "A"
STR_0015 ASCII "B"
STR_0016 ASCII "C"
STR_0017 ASCII "H" * unreferenced
STR_0018 ASCII "I"
STR_0019 ASCII "S"
STR_001A ASCII "V"
STR_001B ASCII "X"
STR_001C ASCII "PUL"
STR_001E ASCII "PSH"
STR_0020 ASCII "," * unreferenced
STR_0021 ASCII "-" * unreferenced
STR_0022 ASCII ",X"
STR_0024 ASCII "operand fetch"
STR_002B ASCII "stack read"
STR_0031 ASCII "stack write"
STR_0037 ASCII "halt"
STR_003A ASCII "vector"
STR_003E ASCII "unused"
STR_0042 ASCII "opcode fetch"
STR_0049 ASCII "DMA read"
STR_004E ASCII "DMA write"
STR_0053 ASCII "memory read"
STR_0059 ASCII "memory write"
STR_0060 ASCII "out of synch"
STR_0067 ASCII "interrupt ack"
STR_006E ASCII "Illegal Opcode"
STR_0076 ASCII "unused cycle"
STR_007D ASCII "dma or halt"
STR_0083 ASCII "non valid cycle"
CONST_0042 CONSTANT 00000FFFFH
CONST_0044 CONSTANT 00000FF00H
CONST_0046 CONSTANT 0FFFFFF00H
ENTRY_POINT
IF TASK = 3 THEN GOTO LABEL_0010
IF TASK = 4 THEN GOTO LABEL_0015
IF TASK = 5 THEN GOTO LABEL_0015
OUTPUT "Illegal Task Request"
ABORT
OUTPUT "Data Error"
ABORT
LABEL_000D
POSITION ABS,1
OUTPUT STR_006E * "Illegal Opcode"
ABORT
LABEL_0010
LOAD ID_CODE
IF 7,0 = 0000000F0H THEN GOTO LABEL_0016
GOTO LABEL_0026
LABEL_0015
GOTO LABEL_0016
LABEL_0016
LOAD INPUT_TAG
IF 17,16 = 0 THEN GOTO LABEL_0043
LOAD INPUT_STATUS
IF 2,2 = 1 THEN GOTO LABEL_0043
LOAD INPUT_TAG
CASE_OF 1,0
GOTO LABEL_01A2
GOTO LABEL_0043
GOTO LABEL_0054
NOP
CASE_END
RETURN
LABEL_0026
LOAD INPUT_STATUS
IF 3,0 = 9 THEN GOTO LABEL_005B
LOAD INPUT_DATA
POSITION ABS,3
OUTPUT ACCUMULATOR,FMT_0012
POSITION REL,1
LOAD INPUT_STATUS
CASE_OF 3,0
OUTPUT STR_006E * "Illegal Opcode"
OUTPUT STR_0024 * "operand fetch"
OUTPUT STR_002B * "stack read"
OUTPUT STR_0031 * "stack write"
OUTPUT STR_002B * "stack read"
OUTPUT STR_0031 * "stack write"
OUTPUT STR_0037 * "halt"
OUTPUT STR_003A * "vector"
OUTPUT STR_003E * "unused"
OUTPUT STR_0042 * "opcode fetch"
OUTPUT STR_0049 * "DMA read"
OUTPUT STR_004E * "DMA write"
OUTPUT STR_0059 * "memory write"
OUTPUT STR_0053 * "memory read"
OUTPUT STR_0060 * "out of synch"
OUTPUT STR_0067 * "interrupt ack"
CASE_END
SET RETURN_FLAGS,0
RETURN
LABEL_0043
LOAD INPUT_DATA
POSITION ABS,3
OUTPUT ACCUMULATOR,FMT_0012
POSITION REL,1
LOAD INPUT_STATUS
CASE_OF 2,0
OUTPUT STR_0083 * "non valid cycle"
OUTPUT STR_0083 * "non valid cycle"
OUTPUT STR_0059 * "memory write"
OUTPUT STR_0053 * "memory read"
OUTPUT STR_007D * "dma or halt"
OUTPUT STR_007D * "dma or halt"
OUTPUT STR_007D * "dma or halt"
OUTPUT STR_007D * "dma or halt"
CASE_END
SET RETURN_FLAGS,0
RETURN
LABEL_0054
LOAD INPUT_DATA
POSITION ABS,3
OUTPUT ACCUMULATOR,FMT_0012
POSITION REL,1
OUTPUT STR_0076 * "unused cycle"
SET RETURN_FLAGS,0
RETURN
LABEL_005B
SET RETURN_FLAGS,1
INPUT REL,0
LOAD INITIAL_DATA
CASE_OF 7,7
GOTO LABEL_0062
GOTO LABEL_0103
CASE_END
LABEL_0062
CASE_OF 7,4
GOTO LABEL_006C
GOTO LABEL_008C
GOTO LABEL_009F
GOTO LABEL_00C4
GOTO LABEL_00E2
GOTO LABEL_00E2
GOTO LABEL_00E2
GOTO LABEL_00E2
CASE_END
LABEL_006C
CASE_OF 3,0
GOTO LABEL_000D
OUTPUT "NOP"
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "TAP"
OUTPUT "TPA"
OUTPUT "INX"
OUTPUT "DEX"
GOTO LABEL_007F
GOTO LABEL_0081
GOTO LABEL_007F
GOTO LABEL_0081
GOTO LABEL_007F
GOTO LABEL_0081
CASE_END
RETURN
LABEL_007F
OUTPUT "CL"
GOTO LABEL_0082
LABEL_0081
OUTPUT "SE"
LABEL_0082
IF 2,1 = 1 THEN OUTPUT STR_001A * "V"
IF 2,1 = 2 THEN OUTPUT STR_0016 * "C"
IF 2,1 = 3 THEN OUTPUT STR_0018 * "I"
RETURN
LABEL_008C
CASE_OF 3,0
OUTPUT "SBA"
OUTPUT "CBA"
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "TAB"
OUTPUT "TBA"
GOTO LABEL_000D
OUTPUT "DAA"
GOTO LABEL_000D
OUTPUT "ABA"
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
CASE_END
RETURN
LABEL_009F
OUTPUT STR_0015 * "B"
CASE_OF 3,0
OUTPUT "RA"
GOTO LABEL_000D
OUTPUT "HI"
OUTPUT "LS"
OUTPUT "CC"
OUTPUT "CS"
OUTPUT "NE"
OUTPUT "EQ"
OUTPUT "VC"
OUTPUT "VS"
OUTPUT "PL"
OUTPUT "MI"
OUTPUT "GE"
OUTPUT "LT"
OUTPUT "GT"
OUTPUT "LE"
CASE_END
LABEL_00B2
INCREMENT INPUT_ADDRESS
LOAD INPUT_ADDRESS
ADD 1
STORE VAR_003E
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
LOAD INPUT_DATA
POSITION ABS,6
IF 7,7 = 1 THEN INCLUSIVE_OR CONST_0046
ADD VAR_003E
AND CONST_0042
IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
RETURN
LABEL_00C4
CASE_OF 3,0
OUTPUT "TSX"
OUTPUT "INS"
GOTO LABEL_00D7
GOTO LABEL_00D7
OUTPUT "DES"
OUTPUT "TXS"
GOTO LABEL_00D7
GOTO LABEL_00D7
GOTO LABEL_000D
OUTPUT "RTS"
GOTO LABEL_000D
OUTPUT "RTI"
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "WAI"
OUTPUT "SWI"
CASE_END
RETURN
LABEL_00D7
IF 2,2 = 0 THEN OUTPUT STR_001C * "PUL"
IF 2,2 = 1 THEN OUTPUT STR_001E * "PSH"
CASE_OF 0,0
GOTO LABEL_00FF
GOTO LABEL_0101
CASE_END
RETURN
LABEL_00E2
CASE_OF 3,0
OUTPUT "NEG"
GOTO LABEL_000D
GOTO LABEL_000D
OUTPUT "COM"
OUTPUT "LSR"
GOTO LABEL_000D
OUTPUT "ROR"
OUTPUT "ASR"
OUTPUT "ASL"
OUTPUT "ROL"
OUTPUT "DEC"
GOTO LABEL_000D
OUTPUT "INC"
OUTPUT "TST"
GOTO LABEL_00F5
OUTPUT "CLR"
CASE_END
GOTO LABEL_00F9
LABEL_00F5
CASE_OF 5,5
GOTO LABEL_000D
OUTPUT "JMP"
CASE_END
LABEL_00F9
CASE_OF 5,4
GOTO LABEL_00FF
GOTO LABEL_0101
GOTO LABEL_016B
GOTO LABEL_0170
CASE_END
LABEL_00FF
OUTPUT STR_0014 * "A"
RETURN
LABEL_0101
OUTPUT STR_0015 * "B"
RETURN
LABEL_0103
CASE_OF 3,0
OUTPUT "SUB"
OUTPUT "CMP"
OUTPUT "SBC"
GOTO LABEL_000D
OUTPUT "AND"
OUTPUT "BIT"
OUTPUT "LDA"
GOTO LABEL_0116
OUTPUT "EOR"
OUTPUT "ADC"
OUTPUT "ORA"
OUTPUT "ADD"
GOTO LABEL_011E
GOTO LABEL_0126
GOTO LABEL_0138
GOTO LABEL_0141
CASE_END
GOTO LABEL_0150
LABEL_0116
IF 7,4 = 8 THEN GOTO LABEL_000D
IF 7,4 = 12 THEN GOTO LABEL_000D
OUTPUT "STA"
GOTO LABEL_0150
LABEL_011E
IF 7,4 >= 12 THEN GOTO LABEL_000D
OUTPUT "CPX"
IF 5,4 = 0 THEN GOTO LABEL_0161
GOTO LABEL_0156
LABEL_0126
IF 7,4 = 9 THEN GOTO LABEL_000D
IF 7,4 >= 12 THEN GOTO LABEL_000D
IF 5,4 = 0 THEN GOTO LABEL_0136
OUTPUT "JSR"
IF 5,4 = 2 THEN GOTO LABEL_016B
IF 5,4 = 3 THEN GOTO LABEL_0170
LABEL_0136
OUTPUT "BSR"
GOTO LABEL_00B2
LABEL_0138
OUTPUT "LD"
CASE_OF 6,6
OUTPUT STR_0019 * "S"
OUTPUT STR_001B * "X"
CASE_END
IF 5,4 = 0 THEN GOTO LABEL_0161
GOTO LABEL_0156
LABEL_0141
IF 7,4 = 8 THEN GOTO LABEL_000D
IF 7,4 = 12 THEN GOTO LABEL_000D
OUTPUT "ST"
CASE_OF 6,6
OUTPUT STR_0019 * "S"
OUTPUT STR_001B * "X"
CASE_END
IF 5,4 = 0 THEN GOTO LABEL_0161
GOTO LABEL_0156
LABEL_0150
IF 6,6 = 0 THEN CALL LABEL_00FF
IF 6,6 = 1 THEN CALL LABEL_0101
LABEL_0156
CASE_OF 5,4
GOTO LABEL_015C
GOTO LABEL_0166
GOTO LABEL_016B
GOTO LABEL_0170
CASE_END
LABEL_015C
POSITION ABS,6
OUTPUT "#"
CALL LABEL_0175
OUTPUT ACCUMULATOR,FMT_0012
RETURN
LABEL_0161
POSITION ABS,6
OUTPUT "#"
CALL LABEL_017E
OUTPUT ACCUMULATOR,FMT_0010
RETURN
LABEL_0166
POSITION ABS,6
CALL LABEL_0175
IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
RETURN
LABEL_016B
POSITION ABS,6
CALL LABEL_0175
OUTPUT ACCUMULATOR,FMT_0012
OUTPUT STR_0022 * ",X"
RETURN
LABEL_0170
POSITION ABS,6
CALL LABEL_017E
IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
RETURN
LABEL_0175
INCREMENT INPUT_ADDRESS
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
LOAD INPUT_DATA
RETURN
LABEL_017C
OUTPUT "**"
ABORT
LABEL_017E
INCREMENT INPUT_ADDRESS
LOAD INPUT_ADDRESS
STORE VAR_003C
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_0192
LOAD INPUT_DATA
ROTATE LEFT,8
AND CONST_0044
STORE VAR_0034
INCREMENT INPUT_ADDRESS
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_019D
LOAD INPUT_DATA
AND 0000000FFH
INCLUSIVE_OR VAR_0034
RETURN
LABEL_0192
OUTPUT "**"
LOAD VAR_003C
STORE INPUT_ADDRESS
INCREMENT INPUT_ADDRESS
INPUT ABS,INPUT_ADDRESS
IF INPUT_ERROR <> 0 THEN GOTO LABEL_01A0
LOAD INPUT_DATA
OUTPUT ACCUMULATOR,FMT_0012
ABORT
LABEL_019D
LOAD VAR_0034
ROTATE RIGHT,8
OUTPUT ACCUMULATOR,FMT_0012
LABEL_01A0
OUTPUT "**"
ABORT
LABEL_01A2
SET VAR_0040,0
LABEL_01A3
LOAD INPUT_STATUS
IF 1,0 = 3 THEN GOTO LABEL_01AE
TAG_WITH 2
INCREMENT VAR_0040
INPUT REL,VAR_0040
IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
GOTO LABEL_01A3
LABEL_01AE
LOAD INPUT_DATA
CASE_OF 7,0
GOTO LABEL_000D
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
LOAD 0000003A8H
LOAD 0000003A8H
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
GOTO LABEL_000D
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 0000003A4H
GOTO LABEL_000D
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A4H
LOAD 0000003A8H
LOAD 0000003A8H
LOAD 000000368H
LOAD 000000368H
LOAD 0000003A8H
LOAD 0000003A8H
LOAD 000000398H
LOAD 000000398H
GOTO LABEL_000D
LOAD 000000D68H
GOTO LABEL_000D
LOAD 000355568H
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 00D695558H
LOAD 003595558H
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
LOAD 56
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 56
GOTO LABEL_000D
LOAD 56
LOAD 00000D9A4H
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 00000D9A4H
LOAD 00000D9A4H
GOTO LABEL_000D
LOAD 00000D9A4H
LOAD 00000D9A4H
LOAD 00000D9A4H
LOAD 00000D9A4H
LOAD 00000D9A4H
GOTO LABEL_000D
LOAD 00000D9A4H
LOAD 00000EAA4H
LOAD 0000003A4H
LOAD 00000D9A4H
LOAD 000003654H
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 000003654H
LOAD 000003654H
GOTO LABEL_000D
LOAD 000003654H
LOAD 000003654H
LOAD 000003654H
LOAD 000003654H
LOAD 000003654H
GOTO LABEL_000D
LOAD 000003654H
LOAD 000003A54H
LOAD 0000000D4H
LOAD 000003654H
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
LOAD 52
LOAD 0000000D4H
LOAD 00003A964H
LOAD 0000000D4H
GOTO LABEL_000D
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
GOTO LABEL_000D
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 000000364H
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 000000354H
GOTO LABEL_000D
LOAD 000000354H
LOAD 000000D64H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
GOTO LABEL_000D
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 0000036A4H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 0000035A4H
LOAD 00003A964H
LOAD 0000035A4H
LOAD 00000D6A4H
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
GOTO LABEL_000D
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
LOAD 000000D94H
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
LOAD 000000D54H
LOAD 0000EA594H
LOAD 000000D54H
LOAD 000003594H
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
LOAD 52
LOAD 52
LOAD 52
LOAD 52
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 0000000D4H
GOTO LABEL_000D
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
GOTO LABEL_000D
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 000000364H
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
LOAD 0000000D4H
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 000000354H
LOAD 000000D64H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
GOTO LABEL_000D
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 0000036A4H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
LOAD 000000DA4H
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 0000035A4H
LOAD 00000D6A4H
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
GOTO LABEL_000D
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
LOAD 000000D94H
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
LOAD 000000354H
GOTO LABEL_000D
GOTO LABEL_000D
LOAD 000000D54H
LOAD 000003594H
CASE_END
LABEL_02B1
STORE VAR_0036
AND 3
STORE VAR_003A
IF 1,0 = 3 THEN GOTO LABEL_005B
TAG_WITH VAR_003A
LABEL_02B8
INCREMENT VAR_0040
INPUT REL,VAR_0040
IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
LOAD INPUT_STATUS
IF 2,2 = 1 THEN GOTO LABEL_02B8
LOAD VAR_0036
ROTATE RIGHT,2
GOTO LABEL_02B1
1 "IAL"
2
0000 3 ENTRY_POINT
0000 00000000 4 NOP
0001 0014 5 TRACE_ON * ION_TRACE = 20
0002 0015 6 TRACE_OFF * IOFF_TRACE = 21
0003 0018 7 MARK_LINE OTHER,NO_ADDRESS * IMARKLINE_O_NA = 24
0004 0019 8 MARK_LINE SOURCE,NO_ADDRESS * IMARKLINE_S_NA = 25
0005 001A 9 MARK_LINE OTHER * IMARKLINE_O_A = 26
0006 001B 10 MARK_LINE SOURCE * IMARKLINE_S_A = 27
0007 001C 11 MARK_STATE DISPLAYED * IMARKSTATE_DISP = 28
0008 001D 12 MARK_STATE SUPPRESSED * IMARKSTATE_SUP = 29
0009 0013 13 RETURN
IA File: IHPIB_I
IA Description: "HPIB IA FOR INTERFACE 1_0"
IA Field Option: A
IA File: IRS232_I
IA Description: "RS232 IA FOR INTERFACE 1_0"
IA Field Option: A
IA File: IRS449_I
IA Description: "RS449 IA FOR INTERFACE 1_0"
IA Field Option: A
BTW, I'm not sure the license file - "The 16700 analyzers have the B4620B Software Correlation Tool option. The analyzer comes with the tool installed, but needs a license to use. Fortunately, the license file is available for non-commercial use (along with licenses for the other options)." - mentioned above made the transition from Yahoo groups to groups.io.The license file is text. The content of the file is embedded in a post, so it got moved from yahoo and it's still there.
Can anyone point to a copy of it? I'll be happy to add it to Groups.io Agilent group
...I don't have a 1670 series to directly help with the issue you're seeing, but you might try loading the configuration file c68010_p instead. In my reading of the manual, I think loading the configuration file should automatically load the associated inverse assembler after it has processed the configuration. Maybe there's some other setup it needs to perform first.
And then "load analyzer from i68010_p" it flashes the asterisk in the top right but nothing seems to happen and when I go to config or waveform or listing I don't see anything... What am I missing?
Thanks, Mike
I don't have a 1670 series to directly help with the issue you're seeing, but you might try loading the configuration file c68010_p instead. In my reading of the manual, I think loading the configuration file should automatically load the associated inverse assembler after it has processed the configuration. Maybe there's some other setup it needs to perform first.
The configuration files in that zip file are for a 16510 analyzer, but the manual says the 1670G should be able to read them.
Perhaps someone with a 1670 (or 16510) could help out more.
:SELECT 1
:MACHINE1:NAME '68010'
:MACHINE1:ASSIGN 1,2,3,4
:MACHINE1:TYPE STATE
:MACHINE2:TYPE OFF
:MACHINE1:SFORMAT:MASTER J, RISING
:MACHINE1:SFORMAT:REMOVE ALL
:MACHINE1:SFORMAT:LABEL 'ADDR', POSITIVE, #H0, #H0000, #HFF00, #HFFFF, #H0000
:MACHINE1:SFORMAT:LABEL 'DATA', POSITIVE, #H0, #H0000, #H0000, #H0000, #HFFFF
:MACHINE1:SFORMAT:LABEL 'STAT', POSITIVE, #H0, #H0000, #H00FF, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'SIZE', POSITIVE, #H0, #H0000, #H0006, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'VMA', POSITIVE, #H0, #H0000, #H0008, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'FC', POSITIVE, #H0, #H0000, #H0070, #H0000, #H0000
:MMEMORY:CD '\INVASMV3', INTERNAL0
:MMEMORY:LOAD:IASSEMBLER 'I68010_P', INTERNAL0, 1, 1
:MMEMORY:CD '\', INTERNAL0
:MACHINE1:SYMBOL:REMOVE
:MACHINE1:SYMBOL:WIDTH 'STAT', 15
:MACHINE1:SYMBOL:BASE 'STAT', BINARY
:MACHINE1:SYMBOL:PATTERN 'STAT', 'DMA', '#B0XXXXXXX'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER DATA WRITE', '#B1001XXX0'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER DATA READ', '#B1001XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER PGRM READ', '#B1010XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR DATA WRITE', '#B1101XXX0'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR DATA READ', '#B1101XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR PGRM READ', '#B1110XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'INTERRUPT ACK', '#B1111XXXX'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'OPCODE FETCH', '#B1X10XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'READ', '#BXXXXXXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'WRITE', '#BXXXXXXX0'
:MACHINE1:SYMBOL:WIDTH 'SIZE', 9
:MACHINE1:SYMBOL:BASE 'SIZE', BINARY
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'LOW BYTE', '#B10'
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'HIGH BYTE', '#B01'
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'WORD', '#B00'
:MACHINE1:SYMBOL:WIDTH 'VMA', 10
:MACHINE1:SYMBOL:BASE 'VMA', BINARY
:MACHINE1:SYMBOL:PATTERN 'VMA', '6800 CYCLE', '#B1'
:MACHINE1:SYMBOL:PATTERN 'VMA', '', '#B0'
:MACHINE1:SYMBOL:WIDTH 'FC', 9
:MACHINE1:SYMBOL:BASE 'FC', BINARY
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER DATA', '#B001'
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER PROG', '#B010'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR DATA', '#B101'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR PROG', '#B110'
:MACHINE1:SYMBOL:PATTERN 'FC', 'INTR ACK', '#B111'
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER', '#B0XX'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR', '#B1XX'
:MACHINE1:SYMBOL:PATTERN 'FC', ' DATA', '#BX01'
:MACHINE1:SYMBOL:PATTERN 'FC', ' PROG', '#BX10'
:MACHINE1:STRIGGER:CLEAR ALL
:MACHINE1:SLIST:REMOVE
:MACHINE1:SLIST:COLUMN 1, 'ADDR', HEXADECIMAL
:MACHINE1:SLIST:COLUMN 2, 'DATA', IASSEMBLER
:MACHINE1:SLIST:COLUMN 3, 'STAT', SYMBOL
:MACHINE1:SLIST:COLUMN 4, 'SIZE', SYMBOL
:MACHINE1:SLIST:COLUMN 5, 'VMA', SYMBOL
:MACHINE1:SLIST:COLUMN 6, 'FC', SYMBOL
:MACHINE1:SWAVEFORM:REMOVE
:MACHINE1:SWAVEFORM:INSERT 'ADDR', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'DATA', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'STAT', OVERLAY
:MENU 1,7
Title: 6809E CONFIG FOR GP PROBES 1_0
Pod assigments (? = disabled)
-----------------------------
Label 0: ADDR (16 bits): A2: ******** ********
Label 1: DATA ( 8 bits): A1: ........ ********
Label 2: STAT ( 3 bits): A1: .....*** ........
Symbols
-------
Label: STAT
INTR/RESET VECTR 01X
SYNC ACKNOWLEDGE 10X
HALT/BUS GRANT 11X
WRITE 000
READ 001
Title: 6809E CONFIG FOR GP PROBES 1_0
Pod assigments (? = disabled)
-----------------------------
Label 0: ADDR (16 bits): A2: ******** ********
Label 1: DATA ( 8 bits): A1: ........ ********
Label 2: STAT ( 3 bits): A1: .....*** ........
Symbols
-------
Label: STAT
INTR/RESET VECTR 01X
SYNC ACKNOWLEDGE 10X
HALT/BUS GRANT 11X
WRITE 000
READ 001
Pod A1: Channel 8 is to pin 32 of 6809E (R//W)
Pod A1: Channel 9 is to pin 5 of 6809E (BS)
Pod A1: Channel 10 is to pin 6 of 6809E (BA)
Pod A1: Clk is to pin 34 of 6809E (E) (Still unsure about this one...)
Is this correct?
Why isn't the address advancing? It goes all the way to 4095 in the list. RESET isn't LOW.
I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.
For example it contains this instruction opcode table. The opcode bit field positions vary in the instruction word based on the values of high order bits in the instruction word.Code: [Select]/* definitions for the different unique bit patterns for each instruction
* in the different instruction groups -- used by the interpreter
*/
I had a similar problem loading the C6800/02.I file on my HP 16500.
I solved it by manually creating the 6800 mapping from gslick's screenshots in this thread, including the User Symbols, making sure the machine name was 6800/02, then saving to the C6800/02 IA file. Another file was created with that same name but newer timestamp - it was bigger, and also created a new config.txt file with that name. Then I could power cycle my HP16500B and load the C6800/02.I file successfully. I only had to change the User Symbol table back to Binary to see the symbols I had entered.
/* instruction group 1 */
const u_int16 IF_OP = 4;
const u_int16 IF_BITS = 5;
const u_int16 ICASE_OP = 6;
const u_int16 ICASE_BITS = 7;
/* instruction group 2 */
const u_int16 IGO_TO = 4;
const u_int16 ICALL = 5;
const u_int16 ISTR_OUTPUT = 6;
const u_int16 INUM_OUTPUT = 7;
/* instruction group 3 */
const u_int16 ILOAD_ACC = 8;
const u_int16 IADD_ACC = 9;
const u_int16 ISUB_ACC = 10;
const u_int16 IAND_ACC = 11;
const u_int16 IOR_ACC = 12;
const u_int16 IXOR_ACC = 13;
const u_int16 ITAG_WITH = 14;
const u_int16 INP_ABS = 15;
/* instruction group 4 */
const u_int16 ISTORE_MEM = 4;
const u_int16 INC_MEM = 5;
const u_int16 IDEC_MEM = 6;
const u_int16 INP_ABSQ = 7;
/* instruction group 5 */
const u_int16 INP_REL = 2;
const u_int16 INP_RELQ = 3;
/* instruction group 6 */
const u_int16 IROT_LEFT = 8;
const u_int16 IROT_RIGHT = 9;
const u_int16 IEXT_BIT = 10;
const u_int16 IPOS_ABS = 11;
const u_int16 IPOS_REL = 12;
/* instruction group 7 */
const u_int16 INOP = 16;
const u_int16 ICOMP_ACC = 17;
const u_int16 ITWOCOMP_ACC = 18;
const u_int16 IRETURN = 19;
const u_int16 ION_TRACE = 20;
const u_int16 IOFF_TRACE = 21;
const u_int16 IABORT = 22;
const u_int16 IFNOT_MAP = 23;
const u_int16 IMARKLINE_O_NA = 24;
const u_int16 IMARKLINE_S_NA = 25;
const u_int16 IMARKLINE_O_A = 26;
const u_int16 IMARKLINE_S_A = 27;
const u_int16 IMARKSTATE_DISP = 28;
const u_int16 IMARKSTATE_SUP = 29;
const u_int16 INEWLINE = 30;
const u_int16 IFETCH_POSITION = 31;
If I have this correct, the mapping from opcode words to instructions in .R files is the following:Code: [Select]/* instruction group 1 */
/* conditional instruction -- bit 15 is set */
/* instruction = (opcode >> 13) */
100x xxxx xxxx xxxx IF_OP = 4
101x xxxx xxxx xxxx IF_BITS = 5
110x xxxx xxxx xxxx ICASE_OP = 6
111x xxxx xxxx xxxx ICASE_BITS = 7
/* instruction group 2 */
/* transfer/output instruction -- bit 14 is set */
/* instruction = (opcode >> 12) */
0100 xxxx xxxx xxxx IGO_TO = 4
0101 xxxx xxxx xxxx ICALL = 5
0110 xxxx xxxx xxxx ISTR_OUTPUT = 6
0111 xxxx xxxx xxxx INUM_OUTPUT = 7
/* set immediate instruction -- bit 13 is on */
001x xxxx xxxx xxxx
/* instruction group 3 */
/* math instruction -- bit 12 is on */
/* instruction = (opcode >> 9) */
0001 000x xxxx xxxx ILOAD_ACC = 8
0001 001x xxxx xxxx IADD_ACC = 9
0001 010x xxxx xxxx ISUB_ACC = 10
0001 011x xxxx xxxx IAND_ACC = 11
0001 100x xxxx xxxx IOR_ACC = 12
0001 101x xxxx xxxx IXOR_ACC = 13
0001 110x xxxx xxxx ITAG_WITH = 14
0001 111x xxxx xxxx INP_ABS = 15
/* instruction group 4 */
/* single variable instruction -- bit 11 is on */
/* instruction = (opcode >> 9) */
0000 100x xxxx xxxx ISTORE_MEM = 4
0000 101x xxxx xxxx INC_MEM = 5
0000 110x xxxx xxxx IDEC_MEM = 6
0000 111x xxxx xxxx INP_ABSQ = 7
/* instruction group 5 */
/* input relative instruction -- bit 10 is on */
/* instruction = (opcode >> 9) */
0000 010x xxxx xxxx INP_REL = 2
0000 011x xxxx xxxx INP_RELQ = 3
/* instruction group 6 */
/* single operand instruction -- bit 9 is on */
/* instruction = (opcode >> 6) */
0000 0010 00xx xxxx IROT_LEFT = 8
0000 0010 01xx xxxx IROT_RIGHT = 9
0000 0010 10xx xxxx IEXT_BIT = 10
0000 0010 11xx xxxx IPOS_ABS = 11
0000 0011 00xx xxxx IPOS_REL = 12
/* instruction group 7 */
/* implied operand instruction - bits 15-5 off, bit 4 on */
0000 0000 0001 0000 INOP = 16
0000 0000 0001 0001 ICOMP_ACC = 17
0000 0000 0001 0010 ITWOCOMP_ACC = 18
0000 0000 0001 0011 IRETURN = 19
0000 0000 0001 0100 ION_TRACE = 20
0000 0000 0001 0101 IOFF_TRACE = 21
0000 0000 0001 0110 IABORT = 22
0000 0000 0001 0111 IFNOT_MAP = 23
0000 0000 0001 1000 IMARKLINE_O_NA = 24
0000 0000 0001 1001 IMARKLINE_S_NA = 25
0000 0000 0001 1010 IMARKLINE_O_A = 26
0000 0000 0001 1011 IMARKLINE_S_A = 27
0000 0000 0001 1100 IMARKSTATE_DISP = 28
0000 0000 0001 1101 IMARKSTATE_SUP = 29
0000 0000 0001 1110 INEWLINE = 30
0000 0000 0001 1111 IFETCH_POSITION = 31
Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.The adapters look nice but I think they are not designed to match the wiring the inverse assembler expects. i.e. the original HP
I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/ (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/)) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.
A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.
I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.
Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.
Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.Installation guide: https://www.keysight.com/upload/cmc_upload/All/16700710.pdf (https://www.keysight.com/upload/cmc_upload/All/16700710.pdf)
I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/ (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/)) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.
A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.
I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.
Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.
Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?Sorry, the adapter information was for the Z80: https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485 (https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485)
Oh - in regard to the 6502 adapter - is there a schematic available? Or does anyone have one that can be reverse engineered? I'm happy to throw a board together once I know what logic is required. I'll check the config files that have been generated for the pin info.
Trying to find an original 6502 adapter would be pretty tough going I expect.
EDIT : It appears that there is no 6502 inverse assembler within the uploaded files - is it still available somewhere?
Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?It sounds like you might have the "missing pullup resistor" problem, the same as the 167xx series:
...
Interesting - I have a bunch of cheap PS2 mice I purchased a while ago (like 10 for $10 or something silly) that were to be used on the analyser (well, one of them anyway!) but didnt work - hopefully this might fix it :) Will fire up the old girl at the weekend and try get it up and running - I'm very keen to get the 6502 setup working - I'll aim to make an adapter PCB to make it fast to set it up, else its too much of a hassle to connect all the probes. The adapter I linked to earlier seems to have the termination network (2 resistors and a capacitor) per signal but no logic - I guess something along the lines of the Z80 one would be a starting point but it would be nice to find someone who has one and replicate it.Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?It sounds like you might have the "missing pullup resistor" problem, the same as the 167xx series:
...
https://www.eevblog.com/forum/testgear/hp-16702a-mouse/msg374967/#msg374967 (https://www.eevblog.com/forum/testgear/hp-16702a-mouse/msg374967/#msg374967)
Sometimes non-Agilent keyboards and mice work, sometimes they don't.
The 40-pin pod connector is fairly standard. If you want to play with inverse assemblers, make sure to create the adapter following the configuration file pinout for the ADDR, DATA and STAT signals as defined in the inverse assembler configuration file. Connecting the POD pins to a 6502 or Z80 is not that difficult, just 16 address lines, 8 data lines and around 4 stat lines including correct clock combinations.
It is correct, 6502 does not need any additional circuitry. Just the correct pins for STAT, in addition to ADDR and DATA
The signal mapping is completely flexible.
Connect up the pods as you like. But to keep things sane, you should probably assign one pod to the ADDR lines, and one pod to STAT and DATA signals. Preserve the ordering of MSB to LSB for the data and address lines.
...
It is correct, 6502 does not need any additional circuitry. Just the correct pins for STAT, in addition to ADDR and DATA
Thanks TK - is is possible to see your configuration as to which pod pins you used to interface to the 6502? Also did you use the IA from Phil Pemberton or another one?
Its not clear from the .S file which pod pins go where but it does list the input status bits and clocking on the falling edge of phi 2 :
************************************************************************
* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
* _
* 7 R/W
* ___
* 6 RST
* ___
* 5 NMI
* ___
* 4 INT
*
* 3 SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.
*
hi to all and thanks for this epic thread !
I'm new owner of HP 16500A, I have timing/state modules the one with ID 31
When I try to load any invasm ( would like to use it for z80 ) i got SOFTWARE ERROR - Please record these number 0010 0000006E 2000
My unit is with 1MB ram and Operating System v.6.
Thanks
DISK DIRECTORY
DOS Filename Date Time Bytes Description
____________ _______ ________ _______ ________________________________
C68000_P 2Jun20 13:05:19 18944 68000 CONFIG FOR GP PROBES 1_0
C68008_P 2Jun20 13:05:50 18944 68008 CONFIG FOR GP PROBES 1_0
C6800_P 2Jun20 13:06:11 18432 6800/02 CONFIG FOR GP PROBES 1_0
C68010_P 2Jun20 13:06:32 18944 68010 CONFIG FOR GP PROBES 1_0
C6809E_P 2Jun20 13:06:52 18432 6809E CONFIG FOR GP PROBES 1_0
C6809_P 2Jun20 13:07:08 18432 6809 CONFIG FOR GP PROBES 1_0
C8085_P 2Jun20 13:07:29 18432 8085 CONFIG FOR GP PROBES 1_0
I68000_P 2Jun20 13:07:50 9216 68000 IA FOR GP PROBES 1_0
I68008_P 2Jun20 13:08:05 9728 68008 IA FOR GP PROBES 1_0
I6800_P 2Jun20 13:08:21 9216 6800/02 IA FOR GP PROBES 1_0
I68010_P 2Jun20 13:08:37 9984 68010 IA FOR GP PROBES 1_0
I6809E_P 2Jun20 13:08:54 10240 6809E IA FOR GP PROBES 1_0
I6809_P 2Jun20 13:09:09 10240 6809 IA FOR GP PROBES 1_0
I8085_IP 2Jun20 13:09:39 5120 8085 INVERSE ASSEMBLER 1_0
SYSTEM_ 31Oct89 0:02:00 233728 HP16500A System Software V06.00
SYSTEM_031 31Oct89 0:02:00 252160 35MHz State/100MHz Timing V06.00
Attached are decoded Inverse Assembler .S source code files for the 10342B HPIB, RS-232, RS-449 interface.Code: [Select]IA File: IHPIB_I
IA Description: "HPIB IA FOR INTERFACE 1_0"
IA Field Option: A
IA File: IRS232_I
IA Description: "RS232 IA FOR INTERFACE 1_0"
IA Field Option: A
IA File: IRS449_I
IA Description: "RS449 IA FOR INTERFACE 1_0"
IA Field Option: A
I'm trying to hook up my HP 10342B HPIB preprocessor to my 16500 logic analyzer.
I loaded the IHPIB_I file onto the SSD replacement for the hard disk.
Now I'm looking for the CHPIB_I configuration file listed in the 10342B manual.
Does anyone have the config file?
19,712 CHPIB_51
19,712 CHPIB_I
19,712 CRS232_51
19,712 CRS232_I
19,712 CRS449_51
19,712 CRS449_I
3,584 IHPIB_I
13,056 IRS232_I
13,056 IRS449_I
I'm trying to hook up my HP 10342B HPIB preprocessor to my 16500 logic analyzer.
I loaded the IHPIB_I file onto the SSD replacement for the hard disk.
Now I'm looking for the CHPIB_I configuration file listed in the 10342B manual.
Does anyone have the config file?
Rather than trying to find another copy of these files posted somewhere else it's quicker to just attach another copy of the 10342B files here:Code: [Select]19,712 CHPIB_51
19,712 CHPIB_I
19,712 CRS232_51
19,712 CRS232_I
19,712 CRS449_51
19,712 CRS449_I
3,584 IHPIB_I
13,056 IRS232_I
13,056 IRS449_I
I used ALLPCB's free service to do a little board for the 65C02. The free boards are a little limited so the signal return path isnt ideal, but can't be too much worse than using the single ground on the pods. Has the termination network on the underside. Will be interesting to give this a go. It should make it very fast to set up the analyser!
I used ALLPCB's free service to do a little board for the 65C02. The free boards are a little limited so the signal return path isnt ideal, but can't be too much worse than using the single ground on the pods. Has the termination network on the underside. Will be interesting to give this a go. It should make it very fast to set up the analyser!
Would it be any easier to layout and build the PCB if it was designed to use a couple of 01650-63203 termination adapters? Then it wouldn't need the termination network on the PCB.
I suppose that wouldn't do any good for anyone that doesn't have any of the 01650-63203 termination adapters. I happen to have a whole box full of them.
10342B HP-IB HEADER conn pinout
10342B GPIB 10342B
Header pin# Header
Name Pin# _____ Pin# Name
| |
ATN 1 |11 7 | 13 NFRD
SRQ 2 |10 6 | 14 DAV
IFC 3 |9 17| 15 REN
NDAC 4 |8 5 | 16 EOI
DIO8 5 |16 15| 17 DIO7
DIO6 6 |14 18| 18 GND
DIO5 7 |13 19| 19 GND
DIO4 8 |4 20| 20 GND
DIO3 9 |3 21| 21 GND
DIO2 10 |2 22| 22 GND
DIO1 11 |1 23| 23 GND
N/C 12 |12 24| 24 GND
|_____|
This pinout is substantially different than the pinout arrangement of a GPIB connector (rectangle in center of my diagram), so possibly the proper HP cable used a PCB mount GPIB connector, see attached image of a GPIB connector (cable end):
10342B Internal Timing POD Header J9
D1 ATN
D2 SRQ
D3 IFC
D4 NDAC
D5 NRFD
D6 DAV
D7 REN
D8 EOI
10342B Front Panel HP-IB Header Connections to Internal Header J9
D1 D5
D2 D6
D3 D7
D4 D8
EOI REN
DAV GND
NRFD GND
NDAC GND
IFC GND
SRC GND
ATN GND
N/C GND
* * (Pins not populated on the 26-pin header)
I've been using the adapter I made along with the 65C02 inverse assembler - works great!
I did however discover a bug in the inverse assembler branch calculation. I wonder if source is still available to be able to fix this?
-159 D010 00
-158 0000 00 memory read
-157 D011 F0 BEQ $D01D (+$05)
-156 D012 05
-155 D013 5D memory read
-154 D018 9D STA $0100, x
see above - the BEQ calculation that calculates the branch to $D01D - should be $D018 which is where the cpu actually branches to as can be seen as the next executed address.
*** Output a relative address
OUTPUT_REL_ADDR
CALL READ_OPERAND
STORE RELTEMP
STORE RELTEMP2
IF 7,7 = 1 THEN GOTO RELA_NEGATIVE
RELA_POSITIVE
* relative addr is positive
ADD INPUT_ADDRESS
ADD 01h
ADD RELTEMP
GOTO RELA_DONE
AND 0FFFFh
RELA_NEGATIVE
* relative addr is negative
TWOS_COMPLEMENT
AND 07Fh
STORE RELTEMP
LOAD INPUT_ADDRESS
SUBTRACT RELTEMP
ADD 01h
AND 0FFFFh
RELA_DONE
CALL ADDR_MAP * display either the address or a symbol
RELA_ADR
LOAD RELTEMP2
IF 7,7 = 0 THEN OUTPUT " (+$"
IF 7,7 = 1 THEN OUTPUT " (-$"
IF 7,7 = 1 THEN TWOS_COMPLEMENT
OUTPUT ACCUMULATOR,HEX7_FMT
OUTPUT ")"
RETURN
-157 D011 F0 BEQ $D01D (+$05) D011 -154.544 us F0 11111 1
-156 D012 05 D012 -153.560 us 05 11110 1
-155 D013 5D memory read D013 -152.576 us 5D 11110 1
-154 D018 9D STA $0100, x D018 -151.592 us 9D 11111 1
...
-145 D01E F0 BEQ $D02A (+$05) D01E -142.752 us F0 11111 1
-144 D01F 05 D01F -141.768 us 05 11110 1
-143 D020 5D memory read D020 -140.784 us 5D 11110 1
-142 D025 9D STA $0200, x D025 -139.800 us 9D 11111 1
...
-133 D02B F0 BEQ $D037 (+$05) D02B -130.960 us F0 11111 1
-132 D02C 05 D02C -129.976 us 05 11110 1
-131 D02D 5D memory read D02D -128.992 us 5D 11110 1
-130 D032 9D STA $0100, x D032 -128.008 us 9D 11111 1
...
-121 D038 F0 BEQ $D044 (+$05) D038 -119.168 us F0 11111 1
-120 D039 05 D039 -118.048 us 05 11110 1
-119 D03A 5D memory read D03A -117.064 us 5D 11110 1
-118 D03F 9D STA $0400, x D03F -116.080 us 9D 11111 1
Comparing files I6502 and I6502X
0000232D: 12 00
0000232E: 1F 10
00002331: B6 A4
00002332: 8D 7E
LABEL_02C7
CALL LABEL_0328
STORE VAR_003E
STORE VAR_0040
IF 7,7 = 1 THEN GOTO LABEL_02D2
ADD INPUT_ADDRESS
ADD 1
NOP
GOTO LABEL_02D9
AND 00000FFFFH
State Number ADDR 6502 mnemonic ADDR Time DATA STAT RW RST NMI INT SYNC RDY VP ML
Decimal Hex Hex Hex Absolute Hex Binary Binary Binary Binary Binary Binary Binary Binary Binary
____________ ____ ________________________________ _______ ___________ ____ ______ ______ ______ ______ ______ ______ ______ ______ ______
21 D00E DD CMP $0000, x D00E 20.632 us DD 11111 1 1 1 1 1 1 0 1
22 D00F 00 D00F 21.616 us 00 11110 1 1 1 1 0 1 0 1
23 D010 00 D010 22.600 us 00 11110 1 1 1 1 0 1 0 1
24 0000 00 memory read 0000 23.576 us 00 11110 1 1 1 1 0 1 0 1
25 D011 F0 BEQ $D018 (+$05) D011 24.560 us F0 11111 1 1 1 1 1 1 0 1
26 D012 05 D012 25.544 us 05 11110 1 1 1 1 0 1 0 1
27 D013 5D memory read D013 26.528 us 5D 11110 1 1 1 1 0 1 0 1
28 D018 9D STA $0100, x D018 27.512 us 9D 11111 1 1 1 1 1 1 0 1
29 D019 00 D019 28.496 us 00 11110 1 1 1 1 0 1 0 1
30 D01A 01 D01A 29.472 us 01 11110 1 1 1 1 0 1 0 1
31 0100 34 memory read 0100 30.456 us 34 11110 1 1 1 1 0 1 0 1
32 0100 00 memory write 0100 31.440 us 00 01110 0 1 1 1 0 1 0 1
33 D01B DD CMP $0100, x D01B 32.424 us DD 11111 1 1 1 1 1 1 0 1
34 D01C 00 D01C 33.408 us 00 11110 1 1 1 1 0 1 0 1
35 D01D 01 D01D 34.384 us 01 11110 1 1 1 1 0 1 0 1
36 0100 00 memory read 0100 35.368 us 00 11110 1 1 1 1 0 1 0 1
37 D01E F0 BEQ $D025 (+$05) D01E 36.352 us F0 11111 1 1 1 1 1 1 0 1
38 D01F 05 D01F 37.336 us 05 11110 1 1 1 1 0 1 0 1
39 D020 5D memory read D020 38.320 us 5D 11110 1 1 1 1 0 1 0 1
40 D025 9D STA $0200, x D025 39.304 us 9D 11111 1 1 1 1 1 1 0 1
41 D026 00 D026 40.280 us 00 11110 1 1 1 1 0 1 0 1
42 D027 02 D027 41.264 us 02 11110 1 1 1 1 0 1 0 1
43 0200 00 memory read 0200 42.248 us 00 11110 1 1 1 1 0 1 0 1
44 0200 00 memory write 0200 43.232 us 00 01110 0 1 1 1 0 1 0 1
45 D028 DD CMP $0200, x D028 44.208 us DD 11111 1 1 1 1 1 1 0 1
46 D029 00 D029 45.192 us 00 11110 1 1 1 1 0 1 0 1
47 D02A 02 D02A 46.176 us 02 11110 1 1 1 1 0 1 0 1
48 0200 00 memory read 0200 47.160 us 00 11110 1 1 1 1 0 1 0 1
49 D02B F0 BEQ $D032 (+$05) D02B 48.144 us F0 11111 1 1 1 1 1 1 0 1
50 D02C 05 D02C 49.128 us 05 11110 1 1 1 1 0 1 0 1
51 D02D 5D memory read D02D 50.104 us 5D 11110 1 1 1 1 0 1 0 1
52 D032 9D STA $0100, x D032 51.088 us 9D 11111 1 1 1 1 1 1 0 1
53 D033 00 D033 52.072 us 00 11110 1 1 1 1 0 1 0 1
54 D034 01 D034 53.056 us 01 11110 1 1 1 1 0 1 0 1
55 0100 00 memory read 0100 54.040 us 00 11110 1 1 1 1 0 1 0 1
56 0100 00 memory write 0100 55.024 us 00 01110 0 1 1 1 0 1 0 1
57 D035 DD CMP $0300, x D035 56.000 us DD 11111 1 1 1 1 1 1 0 1
58 D036 00 D036 56.984 us 00 11110 1 1 1 1 0 1 0 1
59 D037 03 D037 57.968 us 03 11110 1 1 1 1 0 1 0 1
60 0300 00 memory read 0300 58.952 us 00 11110 1 1 1 1 0 1 0 1
61 D038 F0 BEQ $D03F (+$05) D038 59.936 us F0 11111 1 1 1 1 1 1 0 1
62 D039 05 D039 61.056 us 05 11110 1 1 1 1 0 1 0 1
63 D03A 5D memory read D03A 62.040 us 5D 11110 1 1 1 1 0 1 0 1
64 D03F 9D STA $0400, x D03F 63.024 us 9D 11111 1 1 1 1 1 1 0 1
65 D040 00 D040 64.000 us 00 11110 1 1 1 1 0 1 0 1
66 D041 04 D041 64.984 us 04 11110 1 1 1 1 0 1 0 1
67 0400 00 memory read 0400 65.968 us 00 11110 1 1 1 1 0 1 0 1
68 0400 00 memory write 0400 66.952 us 00 01110 0 1 1 1 0 1 0 1
69 D042 DD CMP $0400, x D042 67.936 us DD 11111 1 1 1 1 1 1 0 1
70 D043 00 D043 68.912 us 00 11110 1 1 1 1 0 1 0 1
71 D044 04 D044 69.896 us 04 11110 1 1 1 1 0 1 0 1
72 0400 00 memory read 0400 70.880 us 00 11110 1 1 1 1 0 1 0 1
73 D045 F0 BEQ $D04C (+$05) D045 71.864 us F0 11111 1 1 1 1 1 1 0 1
74 D046 05 D046 72.848 us 05 11110 1 1 1 1 0 1 0 1
75 D047 5D memory read D047 73.832 us 5D 11110 1 1 1 1 0 1 0 1
76 D04C 9D STA $0500, x D04C 74.808 us 9D 11111 1 1 1 1 1 1 0 1
77 D04D 00 D04D 75.792 us 00 11110 1 1 1 1 0 1 0 1
78 D04E 05 D04E 76.776 us 05 11110 1 1 1 1 0 1 0 1
79 0500 00 memory read 0500 77.760 us 00 11110 1 1 1 1 0 1 0 1
80 0500 00 memory write 0500 78.744 us 00 01110 0 1 1 1 0 1 0 1
81 D04F DD CMP $0500, x D04F 79.720 us DD 11111 1 1 1 1 1 1 0 1
82 D050 00 D050 80.704 us 00 11110 1 1 1 1 0 1 0 1
83 D051 05 D051 81.688 us 05 11110 1 1 1 1 0 1 0 1
84 0500 00 memory read 0500 82.672 us 00 11110 1 1 1 1 0 1 0 1
85 D052 F0 BEQ $D059 (+$05) D052 83.656 us F0 11111 1 1 1 1 1 1 0 1
86 D053 05 D053 84.640 us 05 11110 1 1 1 1 0 1 0 1
87 D054 5D memory read D054 85.616 us 5D 11110 1 1 1 1 0 1 0 1
88 D059 9D STA $0600, x D059 86.600 us 9D 11111 1 1 1 1 1 1 0 1
89 D05A 00 D05A 87.584 us 00 11110 1 1 1 1 0 1 0 1
90 D05B 06 D05B 88.568 us 06 11110 1 1 1 1 0 1 0 1
91 0600 00 memory read 0600 89.552 us 00 11110 1 1 1 1 0 1 0 1
92 0600 00 memory write 0600 90.528 us 00 01110 0 1 1 1 0 1 0 1
93 D05C DD CMP $0600, x D05C 91.512 us DD 11111 1 1 1 1 1 1 0 1
94 D05D 00 D05D 92.496 us 00 11110 1 1 1 1 0 1 0 1
95 D05E 06 D05E 93.480 us 06 11110 1 1 1 1 0 1 0 1
96 0600 00 memory read 0600 94.464 us 00 11110 1 1 1 1 0 1 0 1
97 D05F F0 BEQ $D066 (+$05) D05F 95.440 us F0 11111 1 1 1 1 1 1 0 1
98 D060 05 D060 96.424 us 05 11110 1 1 1 1 0 1 0 1
99 D061 5D memory read D061 97.408 us 5D 11110 1 1 1 1 0 1 0 1
100 D066 9D STA $0700, x D066 98.392 us 9D 11111 1 1 1 1 1 1 0 1
101 D067 00 D067 99.376 us 00 11110 1 1 1 1 0 1 0 1
102 D068 07 D068 100.360 us 07 11110 1 1 1 1 0 1 0 1
103 0700 00 memory read 0700 101.336 us 00 11110 1 1 1 1 0 1 0 1
104 0700 00 memory write 0700 102.320 us 00 01110 0 1 1 1 0 1 0 1
105 D069 DD CMP $0700, x D069 103.304 us DD 11111 1 1 1 1 1 1 0 1
106 D06A 00 D06A 104.288 us 00 11110 1 1 1 1 0 1 0 1
107 D06B 07 D06B 105.272 us 07 11110 1 1 1 1 0 1 0 1
108 0700 00 memory read 0700 106.256 us 00 11110 1 1 1 1 0 1 0 1
109 D06C F0 BEQ $D073 (+$05) D06C 107.232 us F0 11111 1 1 1 1 1 1 0 1
110 D06D 05 D06D 108.216 us 05 11110 1 1 1 1 0 1 0 1
111 D06E 5D memory read D06E 109.200 us 5D 11110 1 1 1 1 0 1 0 1
112 D073 E8 INX D073 110.184 us E8 11111 1 1 1 1 1 1 0 1
113 D074 D0 memory read D074 111.168 us D0 11110 1 1 1 1 0 1 0 1
114 D074 D0 BNE $D00B (-$6B) D074 112.144 us D0 11111 1 1 1 1 1 1 0 1
115 D075 95 D075 113.128 us 95 11110 1 1 1 1 0 1 0 1
The read from address following the branch instruction is interesting (eg line 27 above) - does the 6502 always read 3 bytes per instruction regardless or is this an IA artifact? I'll have a read of the datasheet plus the source.
Yes, the instructions on how to compile them wrapped in a DLL would be handy too. I read back in the thread and you mentioned you need a specific version of VisualStudio, and that probably has to run on 32 bit WindowsXP.
I happen to have a clean virtual box image of a fresh install of 32 bit WindowsXP, and I could certainly start from there.
Ok, so in my XP VM, I installed visual studio and the 3.67.1008 version of the LA software. I also installed SetupIAAnalysisAddInWizard from the LA CD, and followed the instructions in the readme in the docs folder where that installed to and copied the 3 files into the visual studio folder, but now I'm a bit stumped... what to do from here?
I don't see the Analysis Add In Wizard showing up in the LA software anywhere? Normally I'd just keep playing with this and reading the manuals to figure it out, but I really need to go to bed!
Oh, I see, you use it through visual studio, and you load in a .R file (which I have to figure out how to make). Definitely need to look more at this tomorrow after work :(
To complete the installation of the wizard please copy the three files listed below from:
C:\Program Files\Agilent Technologies\Logic Development\Analysis AddIn Wizard
AgilentAnalysisWizard.ico
AgilentAnalysisWizard.vsdir
AgilentAnalysisWizard.vsz
to:
C:\Program Files\Microsoft Visual Studio .NET 2003\Vc7\vcprojects\
C:\>md 10391B
C:\>xcopy /s X:\IA_Development_Disk 10391B
X:\IA_Development_Disk\ASM.EXE
X:\IA_Development_Disk\IALDOWN.EXE
X:\IA_Development_Disk\INSTALL.BAT
X:\IA_Development_Disk\64700\TABLES\AIAL.txt
X:\IA_Development_Disk\EXAMPLES\68010.BAT
X:\IA_Development_Disk\EXAMPLES\68010.CMD
X:\IA_Development_Disk\EXAMPLES\8085.BAT
X:\IA_Development_Disk\EXAMPLES\8085.CMD
X:\IA_Development_Disk\EXAMPLES\I68010.S
X:\IA_Development_Disk\EXAMPLES\I8085.S
X:\IA_Development_Disk\PROGRAMS\ASM.EXE
X:\IA_Development_Disk\PROGRAMS\IALDOWN.EXE
X:\IA_Development_Disk\TABLES\AIAL.txt
13 File(s) copied
C:\10391B>dir /s /b /a-d
C:\10391B\ASM.EXE
C:\10391B\IALDOWN.EXE
C:\10391B\INSTALL.BAT
C:\10391B\64700\TABLES\AIAL.txt
C:\10391B\EXAMPLES\68010.BAT
C:\10391B\EXAMPLES\68010.CMD
C:\10391B\EXAMPLES\8085.BAT
C:\10391B\EXAMPLES\8085.CMD
C:\10391B\EXAMPLES\I68010.S
C:\10391B\EXAMPLES\I8085.S
C:\10391B\PROGRAMS\ASM.EXE
C:\10391B\PROGRAMS\IALDOWN.EXE
C:\10391B\TABLES\AIAL.txt
C:\10391B>ren C:\10391B\64700\TABLES\AIAL.txt AIAL
C:\10391B>ren C:\10391B\TABLES\AIAL.txt AIAL
C:\10391B>dir /s /b /a-d
C:\10391B\ASM.EXE
C:\10391B\IALDOWN.EXE
C:\10391B\INSTALL.BAT
C:\10391B\64700\TABLES\AIAL
C:\10391B\EXAMPLES\68010.BAT
C:\10391B\EXAMPLES\68010.CMD
C:\10391B\EXAMPLES\8085.BAT
C:\10391B\EXAMPLES\8085.CMD
C:\10391B\EXAMPLES\I68010.S
C:\10391B\EXAMPLES\I8085.S
C:\10391B\PROGRAMS\ASM.EXE
C:\10391B\PROGRAMS\IALDOWN.EXE
C:\10391B\TABLES\AIAL
C:\10391B>CD EXAMPLES
C:\10391B\EXAMPLES>..\ASM I8085.S
asm: Termination, Unimplemented or invalid processor name (line 0)
C:\10391B\EXAMPLES>CD ..
C:\10391B>MD C:\HP64700
C:\10391B>XCOPY /S 64700 C:\HP64700
64700\TABLES\AIAL
1 File(s) copied
C:\10391B\EXAMPLES>DIR /S /B /A-D C:\HP64700
C:\HP64700\TABLES\AIAL
C:\10391B>CD EXAMPLES
C:\10391B\EXAMPLES>..\ASM I8085.S
C:\10391B\EXAMPLES>RD /S /Q C:\HP64700
C:\10391B\EXAMPLES>..\ASM I8085.S
asm: Termination, Unimplemented or invalid processor name (line 0)
C:\10391B\EXAMPLES>SET HPTABLES=C:\10391B\64700\TABLES\
C:\10391B\EXAMPLES>..\ASM I8085.S
C:\10391B\EXAMPLES>..\ASM /OX I8085.S > I8085.LST
Ok, I got it built. I'm just installing the 5.90 version of the logic analyzer software in my VM to see if I can install the addin.
You really have to follow the directions in the manual very carefully. I was trying to figure out why I kept getting a bunch of path errors during the build, and was manually adding folders to the include path in visual studio, but then it got to a header file that just didn't exist, and I was like "WTF???"
Then I read the manual closer - open VS, create the project using the wizard (being sure to visit ALL 3 pages of the wizard), close VS, delete the project file, swap in the other project file, re-open VS, THEN Build. Just a slightly kludgy workaround they had there... ahhh, windows in the 90's / early 2000's - brings back not fond memories...
AdditionalDependencies="agAnalysisAddIn_i.idl;agAnalysisAddIn2_i.idl;"
AdditionalDependencies="agAnalysisAddIn_i.idl;agAnalysisAddIn2_i.idl;agAnalysisAddIn3_i.idl;"
...I'm going to do that. There were a few other things in his store of interest, not to mention a nice metal bristle brush for "Circuit boards and corrosion removal". Just what was needed!
If you want the good one and you want it reasonably quickly, just support Northridge Fix and buy it from him!
...Oops - thanks for noticing that on the quest listing!
You have to be careful though, the one that Quest has for $5.70 each are P08-080-SL??-B-G - the B model is 3mm higher!
At Quest the P08-080-SL??-A that they have in stock is $38 ea.!!!! YIKES
I didn't see that in the first one but I have now downloaded it and looked at it. I have a very old setup using a 486 computer running DOS and VBDOS and the utility looks windows based. All of my gpib access is done through VBDOS. I have been able to read the learn strings to the computer and break them down somewhat into pods, polarities, clocks, state and timing channels, etc. As I was doing this and reading the IA posts about the difficulty in getting original files read from a hp gpib drive loaded into a 1630 machine, I thought that maybe the machine was just being set up a certain way which would be readable, savable, and writable as a learn string configuration file. I was hoping someone on the forum would have a learn string configuration file output from any loaded inverse assembler on a 1630X machine so that I could look and see exactly what settings were being modified so that the assembly language(or machine language) states were captured. In a perfect world it would be on a 1630D or lower machine as I have byte by byte comparison code that shows the differences between two learn strings.
Hopefully, someone might have something close.
Thanks in advance
FWIW are the formats of the various 163X files documented in the programming manual.
In my particular case, I don't have any preprocessor interface for the Z80 (that as far as I understood, processes the control signal from the Z80).
I just have standard flying probes.
Is there a config file and a IA file I can use for this case ? Also, which pins should I use for STAT ?
i would be interested, i guess i need to build a virtual machine so i can build the z80, 6809, 68000 dlls. ( i sourced a 6809 interface )
thanks for sharing!
WooHoo!
Ok, that was a pita to make the 64 bit install files!
gslick, thanks for the tips.. Now to test.
it will be nice to use my bench top 1690D and can retire these old 167X units.
Yes, I had to add agAnalysisAddIn3_i.idl; to the proj file.
On the 1690D:
Windows 10 Pro, 64bit , You need to install the compatibility mode drivers on the 1394 card.
So, now need to make a nice cheat sheet for pod assignments on the 10269CI haven't tried the 80186 IA specifically, but it's been my experience with other processors that A1 -> POD1, etc., as you stated, and in the given bit positions. Some examination of the labels or the disassembled code from gslick may be needed to determine the bit order of STAT and other encoded fields. Fields like ADDR and DATA are MSB -> LSB, as you would expect.
cXXXXX_p.txt will indicate the ADDR/DATA assignments, but not which pod goes where.
ie, what are POD1/2/3/4/5 correlate too for ADDR/DATA/STAT
ie, the 80186 uses
Label 0: ADDR (20 bits): A3: ........ ....**** A2: ******** ********
Label 1: DATA (16 bits): A1: ******** ********
Label 2: STAT (10 bits): A5: .....*** ........ A3: *****.** ........
Label 3: SIZE ( 3 bits): A3: *..*.... ........ A2: ........ .......*
Label 4: S6 ( 1 bits): A3: ..*..... ........
Label 5: COPROC ( 9 bits): A5: .....*** ........ A3: ***.*.** ........
Label 6: DMA CH ( 6 bits): A5: .....*** ........ A3: ***..... ........
Which is 65 bits, but doesn't indicate Which bits are were on POD1/2/3/4/5
the good thing is if your ADDR is 16 bits, but the IA needs 24 Bits, it will tell you !
Are we to assume A1 -> POD1 , A2 -> POD2, A3 -> POD3 ?
also looking at the 80186 ( which is one i just picked out of thin air ) , seems Stat/CoProc/Dma Ch all use the same A5 Pod.. but no A4.. so POD4 shouldn't do anything on the IA module.
I have the Manuals for the z80, 68000 I will try to scan them when i put my hands on them, it has all the pin information in them.
Obviously this isn't needed for the _P IA Options ( non pre-processor )
What do you call those 1-to-4 0.1 pin header breakout connectors? I couldn't guess the correct search term to find them. Where can you get them? I could have used some of those to make it easier to attach the doubled up flying lead connections to the DIP test clip.The part number is HP 16515-27601 "GND CONNECTOR". They're included with the 16517-68701 Master Board Accessory Kit and 16518-68701 Expander Board Accessory Kit., but only two per kit. I haven't seen them anywhere else. They're fairly handy and I'd buy a pile of them if I could find them in quantity.
One interesting thing in my timing capture is that the address lines start changing before the rising edge of /MREQ. When using /MREQ * /IORQ as the only clock, which I tried first, it created nonsensical results in the state capture. This is what led me to look at PHI to do the slave latch capture.
However, in your timing digram, the address lines are stable for at least 80ns (MemRead) to 200ns (OpFetch), leaving plenty of time to use /MREQ * /IORQ in master mode as the only clock (no slave).
With your previous analysis of buffer delays in the Z80 Interface Module:
https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg2525412/#msg2525412 (https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg2525412/#msg2525412)
I'm not sure how this would have ever worked for me, since /MREQ * /IORQ would occur even later because of the buffer delays.
...Going back in my captured data, I also see /WR going high (mumble) 8ns before /MREQ in some cases. For example, the first address byte pushed on the stack in a CALL is that way, but the second address byte has /WR coincident with /MREQ, at least as far as 4ns TZ sampling can tell. (I don't have the system set up anymore to get a more precise delay measurement.)
Delaying the /WR signal before it is sampled at the /MREQ and /IOREQ signal edges as used for the J and K clocks when using the 10300B Z80 preprocessor might be important if the /WR signal transition at the CPU pin can occur before the /MREQ signal transition at the CPU pin.
That appears to be occurring in the trace that I previously acquired when I scrolled forward to a memory write cycle. The rising edge of the /WR signal appears to occur around 3.25ns before the rising edge of the /MREQ signal (with the Timing Zoom sampling resolution of 250ps).
This is great stuff ! Love it.. I have two large driving arcades leaving and going to setup a proper station so i can test things out and dig in and help.
What do you call those 1-to-4 0.1 pin header breakout connectors? I couldn't guess the correct search term to find them. Where can you get them? I could have used some of those to make it easier to attach the doubled up flying lead connections to the DIP test clip.The part number is HP 16515-27601 "GND CONNECTOR". They're included with the 16517-68701 Master Board Accessory Kit and 16518-68701 Expander Board Accessory Kit., but only two per kit. I haven't seen them anywhere else. They're fairly handy and I'd buy a pile of them if I could find them in quantity.
...I saw the first listing and it seemed a bit pricey when you add in shipping, but I didn't know the ground connectors were also provided in the 16515-68703. Thanks!
This eBay listing photo shows two of those 16515-27601 in the item listing photo for $9.95, plus shipping. Not clear if two are included per item purchase, or only one:
Keysight 16515-27601 Ground Connector for 16517-68701 Accessory Kit
https://www.ebay.com/itm/354835319679 (https://www.ebay.com/itm/354835319679)
This eBay listing photo shows four of those in the item listing photo with some ground leads and some sort of probe for $19.95 (OBO), plus shipping. I assume in this listing everything in the item listing photo would be included. Not super cheap, but not an outrageous price if makes things easier to get probes set up.
Keysight 16515-68703 16515A 16516A 1 GHz Timing Probe Accessory Kit
https://www.ebay.com/itm/350517306271 (https://www.ebay.com/itm/350517306271)
Packs a relocatable HP Inverse Assembler into a HFSLIF file structure, suitable
for transferring to a HP Logic Analyzer via FTP. This program provides an
alternative to the HP provided IALDOWN.EXE file, which only supports uploading
via a serial or GPIB connection.
usage:
HFSLIFWriter.exe inputFilePath outputFilePath fileDescription invasmFieldOpt
inputFilePath Path to the relocatable inverse assembler file on disk.
Usually a ".A" file as output by ASM.EXE.
outputFilePath Path to write the generated HFSLIF file to
fileDescription A file description up to 32 characters to display on the logic
analyzer when listing this file on disk.
invasmFieldOpt The control setting for the invasm field. Usage is the same as
in IALDOWN.EXE, a single character of A,B,C or D must be
specified as follows:
A = No "Invasm" Field
B = "Invasm" Field with no pop-up
C = "Invasm" Field with pop-up. 2 choices in pop-up.
D = "Invasm" Field with pop-up. 8 choices in pop-up.