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Offline TimInCanada

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HP Logic Analyzer Inverse Assemblers
« on: May 11, 2018, 06:52:28 pm »
What is an Inverse Assembler (IA), and why would I want one?

If you are using a logic analyzer to watch the address and data buses of a microprocessor, values on the data bus represent the CPU's opcodes and operands which are the addresses and data moving to/from the CPU and I/O and memory.  An inverse assembler is a kind of disassembler that translates bus data into the CPU's assembly language.  It is a piece of software that has to be installed on the analyzer before use.

Modern microprocessors include features such as JTAG for debugging, but vintage microprocessors don't.  A logic analyzer with an IA makes it much easier to reverse engineer or debug an old microcomputer.  It doesn't give you the assembly language source of the program, but instead shows the stream of instructions that are executed and the data they operate on.

As part of the HP 64000 Logic Development System launched in 1979, an "inverse assembler language", IAL, was created and has been used by HP logic analyzers since. An IAL source file has a .S extension.  It is assembled into a .R relocatable file which is formatted for and installed on particular analyzers. 

Operation

A separate IA is required for each microprocessor.  They only operate in the Listing view of State analysis, and just decode the data on the current screen rather than all the acquired data.  The operating manual for each logic analyzer gives the details of how to install an IA.  To use it, the analyzer is connected to the address, data and status buses of the CPU and in the Format menu are given the labels ADDR, DATA, and STAT, respectively.  The IA needs to provide information on how the status lines are to be connected  This is usually in a configuration.txt file.

Once data is acquired, in the Listing view under the label DATA there is a base selector which normally defaults to Hex.   Select the field labeled "Invasm" and the inverse assembler will be activated.

Automatic/Manual Code Detection: Some processors, such as the 6502 and 8085, have status lines which indicate when a byte fetched from memory is code rather than data.  The IA reads the status lines and automatically determines which lines on the display are code.

For other processors, the IA needs to be manually synchronized.  When an IA  that needs manual syncing is loaded there should be a "Invasm" Field displayed on the Listing page.   Scroll the listing up or down until a known code instruction is in the top line,  then select the "Invasm" field.  The IA will start decoding that line as an opcode.  The listing can be scrolled down and the IA will stay in sync, but it will not stay synced when scrolling up.

Naming Conventions

Some of the software that deals with IA files require file names to be 10 characters or less, starting with an upper case letter, letters or numbers or underscore characters only.

The general convention is:
  • First letter of "I" means it is the IA file.
  • First letter of "C" means it is a configuration file.
  • Last letter of "P" means the IA file is for use with general purpose probing (e.g., flying leads).
  • Last letter of "I" means the IA file is for use with dedicated hardware interfaces (often called "preprocessors").

Inverse Assemblers by Processor:
  • invasm_v3.zip contains inverse assemblers for the
    • 6800, 6809
    • 68000, 68008, 68010, 68020
    • 8085, 8086, 8088
    • 80186, 80188, 80286, 80386
    • NSC800
    • Z80 
    In addition to the configuration and IA files, there are relocatable *.R and Invasm Field Option *.info files. (Big thanks to MarkL  :-+)
  • INVASM_SRC.zip contains the decompiled source code for the above IAs.  (Big thanks to gslick  :-+)
  • Details on Z80 STAT bus connections
  • 6502 (includes .S and .R files)
  • 8008 (includes .S and .R files)
  • 10342B_IA.zip contains IAs for the 10342B HPIB, RS-232, RS-449 bus decoder probe.  (Big thanks to gslick  :-+)

Logic Analyzer Notes:

1611A
This is more for historic interest.  The 1611A Logic State Analyzer was described in the January 1977 HP Journal.  It used "personality modules" for each microprocessor that included an IA in ROM.

1630/31

1650/16500/1660/1670

16600/16700
  • Loading preformatted IA files:
    • Copy the IA file into a temporary directory. (Don't forget to set public read permission on the file.)
    • Use the File Manager to load the IA file you just put on the analyzer.
    • The File Manager does necessary formatting and puts its IA file into the  /logic/ia directory.
    • From the Listing screen, select Invasm then Load...
  • If the above doesn't work,
    • Copy a IA relocatable .R version of the file onto the analyzer.
    • Use the  IA Format Utility to convert the file and load it into the /logic/ia directory.
    • From the Listing screen, select Invasm then Load...
1680/1690/16900


Getting IAs onto an analyzer:

Symbol Names

In addition to the IA, a handy tool when working with microprocessors is to create a Symbol Table of known addresses, such as memory-mapped I/O units and variables.  See your analyzer operating manual for specific details of creating a symbol table.

In the Listing display under the label ADDR there is a selection for the base (format) to display addresses in.  The default is usually "Hex".  Change this to  "symbol" and any addresses that are in the symbol table will have their names substituted in the listing.  If a Symbol Table is loaded, the IA will also use these address names in its output.

Source Code Viewer

The 16700 analyzers have the B4620B Software Correlation Tool option.  The analyzer comes with the tool installed, but needs a license to use.  Fortunately, the license file is available for non-commercial use (along with licenses for the other options).

Normally, source code would be compiled with a debug option and after capturing data with the analyzer the source code could be stepped through in the Source viewer while the corresponding line is highlighted in the Listing viewer, and vice-versa.  When reverse engineering old uPs, it is unlikely the source code is available.  However, the Source viewer can still be useful if the uP's code is disassembled into a listing file that gives the addresses of each line of code.  (If a disassembler doesn't create such a listing file, an assembler can be used to re-assemble the disassembled code and generate the listing file.)

The 16700 Help Volume, page 197 gives the General-Purpose ASCII (GPA) Symbol File Format.  The symbol file is just a text file that is placed somewhere on the analyzer's drive and loaded from a Symbols tab. 

Here is an example.  Suppose a piece of assembly code in a listing file called test.lst is:
Code: [Select]
dc19 : b701d0            staa CmdTableIndex
dc1c : 86ee              ldaa #$EE
dc1e : b101d0            cmpa CmdTableIndex
dc21 : 2609              bne LDFAA ; branch if valid CmdChar
dc23 : bdd6c0            jsr subResetCmdFlags
dc26 : 7ee3a0            jmp LE768 ; set flagCmdParse bit6 and rts

The first column is the start address of each line of code.  The symbol file is given a [SOURCE LINES] section, e.g. for this piece of code:
Code: [Select]
[SOURCE LINES]
File: test.lst
...
9029 dc19
9030 dc1c
9031 dc1e
9032 dc21
9033 dc23
9034 dc26
...

The file test.lst is placed in the analyzer's /logic/source/ directory.  The first column is the decimal line number in the source file and the second column is the hexadecimal address.  (A spreadsheet can be used to manually extract the address values and add line numbers, for example.)  The symbol file is loaded in the normal way.   When run to this code, the Listing view will display (at address dc1e):


From the Listing view, on the menu bar at the top of the screen select Source/Open Source Viewer...  The viewer displays the source file and highlights the corresponding source line:


The program execution can be stepped forward and backward and the captured data can be searched to see if particular lines of source were executed.  The listing view shows data values that were passed, for instance, the CMPA (6800 Compare Accumulator A opcode) shows the value 07 was read from memory as the value of variable CmdTableIndex.  In addition, analyzer trigger points can be set at particular lines of the source, similar to breakpoints in emulators and debuggers.  The Listing Display Tool Help Volume pages 24-39 gives details.


Writing an Inverse Assembler

If you wish to write your own IA, the HP 10391B IAL Development Package includes sample source files for the 8085 and 68010 and an assembler to convert the .S source files into .R files for the analyzers.  This software needs to run on a DOS computer or in DOSBOX.  A hint on setting up this assembler.

If anyone has additional files, they can be posted as attachments and links can be added here, too.

Thanks!

Tim
« Last Edit: June 26, 2018, 07:52:40 pm by TimInCanada »
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #1 on: May 11, 2018, 07:51:40 pm »
Been looking for an inverse assembler for the MC6800.  Haven't found one yet, but thought it might be worthwhile to summarize what is available.

The file "invasm.zip" is available in the files section of the "HP/Agilent Test Equipment" Yahoo group if you search for it there in the files section. It is a restricted group and you have to join the group first to access the files section.

https://groups.yahoo.com/neo/groups/hp_agilent_equipment/info
https://groups.yahoo.com/neo/groups/hp_agilent_equipment/files

The file is small enough that I can attach it here. It contains the following set of configuration and inverse assembler files.

c68000_i
c68000_p
c68008_i
c68008_p
c6800_i
c6800_p
c68010_i
c68010_p
c68020_i.p
c6809e_p
c6809_i
c6809_p
c80186e_.i
c80186_i
c80188e_.i
c80188_i
c80286_i
c80386_8.7
c80386_i
c8085_i
c8085_p
c8086_i
c8088_i
cnsc800_.i
cz80_i

i68000_i
i68000_p
i68008_i
i68008_p
i6800_i
i6800_p
i68010_i
i68010_p
i68020_i.p
i6809e_p
i6809_i
i6809_p
i80186e_.i
i80186_i
i80188e_.i
i80188_i
i80286_i
i80386_8.7
i80386_i
i8085_ip
i8086_i
i8088_i
insc800_.i
iz80_i

In the particular case of the 6800 / 6802 CPU the 64672A 10307B preprocessor interface contains a non-trivial state machine that does some decoding of the instruction stream as it is executed to provide addition state information that is not available with the general purpose probe version of the configuration and inverse assembler.
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #2 on: May 11, 2018, 07:59:47 pm »
When the c6800_p 6800 general purpose probe configuration file is loaded into a 16510A analyzer module the configuration is as shown in the attached screen captures.
 
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Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #3 on: May 11, 2018, 10:20:50 pm »
Great summary, Tim, thanks!

I'll add to the party with another zip archive.  gslick, in a different conversation, gave me enough information (thanks, gslick!) that I was able to write a text decoder for the configuration files he just posted in invasm.zip.  Attached here is invasm_configtxt.zip, which is the same as invasm.zip, but includes the text version of the config files (plus the C program that did the decoding).

In the zip file, for processor XXX:

  iXXXp - inverse assember for general (flying lead) probing
  cXXXp - 16510 configuration for general (flying lead) probing
  cXXXp.txt - text 16510 configuration for general (flying lead) probing

  iXXXi - inverse assember for pre-processors
  cXXXi - 16510 configuration for pre-processors
  cXXXi.txt - text 16510 configuration for pre-processors

The significance of having a readable form of the config files is that you now have a fighting chance to use the inverse assemblers on something other than a 16510 card.

For example, I have a 16702B with a 16752A card and I've been successful using it on a 6802 processor.  I can successfully load i6800_p, the inverse assembler for general purpose (flying lead) probes.  No problem there.  However, the IA wants to interpret the bits in the label STAT to determine what machine cycle to display.  The STAT signal assignments are contained in the companion configuration file, c6800_p.  If I had a 16510 it would be easy.

The decoded text of the configuration says:

  Title: 6800/02 CONFIG FOR GP PROBES 1_0
 
  Pod assigments (? = disabled)
  -----------------------------
  Label  0: ADDR     (16 bits):  A2: ******** ******** 
  Label  1: DATA     ( 8 bits):  A1: ........ ******** 
  Label  2: STAT     ( 3 bits):  A1: .....*** ........ 
 
  Symbols
  -------
  Label: STAT 
         INVALID MEM ACCE  00X
         MEMORY WRITE      010
         MEMORY READ       011
         DMA WRITE         1X0
         DMA READ          1X1

From this, and knowing what signals exist on the 6802, it's apparent that:

  STAT[2] = BA (bus available)
  STAT[1] = VMA (valid memory address)
  STAT[0] = R/W (read/not write)

Creating a STAT label and connecting the bits as defined above works, plus the obvious DATA and ADDR labels.  Screen capture attached.  There's other pins being monitored in the capture, but the IA only cares about DATA, ADDR, and STAT.

I haven't tried any of the other processors, but I've spot-checked the decoded configuration against a few processor datasheets and they at least make sense.  Any feedback welcome, success or not, and especially if I got something wrong with the any of the decoded configs.

Perhaps we should add known working STAT assignments to this post, like the 6802 above, for various processors as people figure them out.

The decoded configuration files for pre-processors is also included, although they're probably not very useful unless you have a pre-processor or looking to build one.


EDIT:  I should also add that in the example the clock is the falling edge of the E signal on the 6802 (or phase 2 clock on the 6800).  I haven't decoded the clocking assignments, but like the STAT assignments this could be figured out after a couple of minutes looking at the datasheet.
« Last Edit: May 11, 2018, 10:31:55 pm by MarkL »
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #4 on: May 12, 2018, 12:40:20 am »
To add another note, if you have an IAL style .R relocatable file after the .S file has been run through the assembler, as far as I know there is no simple way to use the .R file with the 16900 series logic analyzer software (also including the 1680 and 1690 series).

However, if you install an older version of the Analysis AddIn Tool there is a wizard tool that lets you build a interpreter wrapper .DLL file around a .R file. It is non-trivial to get set up to do it. The old version of the wizard tool was set up at the time for Microsoft Visual Studio .NET 2003. I did manage to get it set up to build a .DLL file around an assembled .R file from the 8085 .S source from the 10391B tool. I should revisit that and write up some notes about it as I forget exactly what all was involved now.

If you don't have a .R file, or the .S source to build the .R file, I don't know if there is a way to use any of these old IAL style inverse assembler files with the 16900 series logic analyzer software. The files as they are normally distributed are after the IALDOWN tool has done some sort of undocumented transformation of the .R files. Maybe that transformation could be reverse engineered so that a tool could be written to do an inverse transformation back in .R files. Or maybe even disassemble the files back into functionally equivalent .S source files.
 
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Online TK

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #5 on: May 12, 2018, 12:41:08 am »
The STAT bus for the Z80 inverse assembler was described by gslick here: https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485 and it also requires 3 clock signals (missing on the text file).
 
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Offline TimInCanada

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #6 on: May 13, 2018, 08:02:03 pm »
Man, you guys are amazing.  :-+  This is great info.

I just updated the first post.  Please point out any mistakes.  I'm afraid I've got to run.  More later.

Tim
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #7 on: May 14, 2018, 05:53:48 pm »
...
If you don't have a .R file, or the .S source to build the .R file, I don't know if there is a way to use any of these old IAL style inverse assembler files with the 16900 series logic analyzer software. The files as they are normally distributed are after the IALDOWN tool has done some sort of undocumented transformation of the .R files. Maybe that transformation could be reverse engineered so that a tool could be written to do an inverse transformation back in .R files. Or maybe even disassemble the files back into functionally equivalent .S source files.
...
I looked at IALDOWN a while ago hoping it would provide transformation clues for the 1631D:

  https://www.eevblog.com/forum/testgear/searching-for-a-hp-1630-hp-1631-inverse-assembler-files/msg1215139/#msg1215139

In short, all it did was copy the .R file verbatim out the serial port, along with a byte that reflected the user's answer to the number of IA sync states to allow.  This makes me think any transformation/linking happens inside the logic analyzer once the .R file is downloaded.


The .R files appear to have "82 03" for the file magic in the first two bytes.  You can find these bytes in all the iXXX files (at offset 0x227, which includes the 512-byte LIF header).  But unfortunately just extracting that chunk of the file does not seem to make a valid .R file.  The 16700 will happily run IA Format on the extracted piece, but it causes a seg fault when you try to load the result.

Further poking at this shows the IA Format utility only puts a wrapper around whatever file you give it, verbatim.  It also does a couple of sanity checks (maybe looking for 82 03), but it's not going deep enough into the data structures to validate the input.

I was hoping the .R file was still unchanged and sitting inside these iXXX package files, but given the above experiment, unfortunately it's not.  More de-transforming is needed.

Just putting this info out there if anyone wants to dig further.
 

Offline TimInCanada

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #8 on: May 15, 2018, 01:48:00 am »
For example, I have a 16702B with a 16752A card and I've been successful using it on a 6802 processor.  I can successfully load i6800_p, the inverse assembler for general purpose (flying lead) probes. 

Hi Mark,

I've also got a 16702B, with 16712A and 16555A cards, but the i6800_p file isn't working for me.  When I try to use the INVASM function on the Listing screen, it says the file is for a 16500 analyzer and needs to be loaded through the File manager.  The file manager gives an error message about a possible filter problem.  The IA Format utility gives an error message that it's not an "IAL" file. 

I just saw your post mentioning the first two bytes being "82 03" and tried putting those in the file.  The IA Format utility now converts the file, but when trying to load the IA on the listing screen it gives an error about file manager handle not found.

Have you run into any problems like these?

The IA asm.exe file contains the text "@(mktid) 64851S006    USER DEFINABLE ASSEMBLER                 A.02.10 10Mar88 14:20:13" .  64851 happens to be HP-UX Hosted Cross Assembler/Linker User Definable, if that might help in figuring out what it does.

Tim
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #9 on: May 15, 2018, 02:35:22 pm »
Hi Tim,

It's true the IA needs to be loaded through the File Manager.  But you only need to do it once.  Once it's loaded, the analyzer creates a special version for itself in the /logic/ia directory with the same name.  You can then use the Lister "Invasm" pulldown to load the same IA next time around.

And when I say "File Manager", I mean the file manager utility, which is the little folder icon, and not the File pulldown.

Also, before you load it, you should define ADDR, DATA, and STAT fields in the pod Format tab.  If you don't, the IA will complain that those fields don't exist and refuse to load.  It's expecting the configuration to load first and take care of this, but the 16510 config files can't be loaded on this machine.  The IA only cares that the fields exist and have between 1 and 32 bits, so they don't have to be right to start; you can go back and fix them up before doing an actual capture.

I haven't seen any loading errors referring to a "filter", although it will tell you there's no compatible instruments if you try to load the 16510 configuration file (cXXX).  Which IA are you trying?  I haven't tried them all, but I can try the one that's giving you trouble.

I don't think it should matter what card you're using, but this works on 16752A and 16717A cards for me.  I'm running 2.90 which is the latest (and last available) version for the 16702B.


Interesting find on the 64851 User Definable Assembler.  I'm guessing it was used to generate the parsing table that asm.exe uses (in HP64700/TABLES/AIAL).  Maybe 64851 will provide some clues on the .R files.  I'll take a look.
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #10 on: May 15, 2018, 06:46:26 pm »
I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.

For example it contains this instruction opcode table. The opcode bit field positions vary in the instruction word based on the values of high order bits in the instruction word.

Code: [Select]
  /* definitions for the different unique bit patterns for each instruction
   * in the different instruction groups -- used by the interpreter
   */

  /* instruction group 1 */
  const u_int16 IF_OP = 4;
  const u_int16 IF_BITS = 5;
  const u_int16 ICASE_OP = 6;
  const u_int16 ICASE_BITS = 7;

  /* instruction group 2 */
  const u_int16 IGO_TO = 4;
  const u_int16 ICALL = 5;
  const u_int16 ISTR_OUTPUT = 6;
  const u_int16 INUM_OUTPUT = 7;

  /* instruction group 3 */
  const u_int16 ILOAD_ACC = 8;
  const u_int16 IADD_ACC = 9;
  const u_int16 ISUB_ACC = 10;
  const u_int16 IAND_ACC = 11;
  const u_int16 IOR_ACC = 12;
  const u_int16 IXOR_ACC = 13;
  const u_int16 ITAG_WITH = 14;
  const u_int16 INP_ABS = 15;

  /* instruction group 4 */
  const u_int16 ISTORE_MEM = 4;
  const u_int16 INC_MEM = 5;
  const u_int16 IDEC_MEM = 6;
  const u_int16 INP_ABSQ = 7;

  /* instruction group 5 */
  const u_int16 INP_REL = 2;
  const u_int16 INP_RELQ = 3;

  /* instruction group 6 */
  const u_int16 IROT_LEFT = 8;
  const u_int16 IROT_RIGHT = 9;
  const u_int16 IEXT_BIT = 10;
  const u_int16 IPOS_ABS = 11;
  const u_int16 IPOS_REL = 12;

  /* instruction group 7 */
  const u_int16 INOP = 16;
  const u_int16 ICOMP_ACC = 17;
  const u_int16 ITWOCOMP_ACC = 18;
  const u_int16 IRETURN = 19;
  const u_int16 ION_TRACE = 20;
  const u_int16 IOFF_TRACE = 21;
  const u_int16 IABORT = 22;
  const u_int16 IFNOT_MAP = 23;
  const u_int16 IMARKLINE_O_NA = 24;
  const u_int16 IMARKLINE_S_NA = 25;
  const u_int16 IMARKLINE_O_A = 26;
  const u_int16 IMARKLINE_S_A = 27;
  const u_int16 IMARKSTATE_DISP = 28;
  const u_int16 IMARKSTATE_SUP = 29;
  const u_int16 INEWLINE = 30;
  const u_int16 IFETCH_POSITION = 31;

If I have this correct, the mapping from opcode words to instructions in .R files is the following:

Code: [Select]
/* instruction group 1 */
/* conditional instruction -- bit 15 is set */
/* instruction = (opcode >> 13) */

100x xxxx xxxx xxxx     IF_OP = 4
101x xxxx xxxx xxxx     IF_BITS = 5
110x xxxx xxxx xxxx     ICASE_OP = 6
111x xxxx xxxx xxxx     ICASE_BITS = 7

/* instruction group 2 */
/* transfer/output instruction -- bit 14 is set */
/* instruction = (opcode >> 12) */

0100 xxxx xxxx xxxx     IGO_TO = 4
0101 xxxx xxxx xxxx     ICALL = 5
0110 xxxx xxxx xxxx     ISTR_OUTPUT = 6
0111 xxxx xxxx xxxx     INUM_OUTPUT = 7

/* set immediate instruction -- bit 13 is on */

001x xxxx xxxx xxxx

/* instruction group 3 */
/* math instruction -- bit 12 is on */
/* instruction = (opcode >> 9) */

0001 000x xxxx xxxx     ILOAD_ACC = 8
0001 001x xxxx xxxx     IADD_ACC = 9
0001 010x xxxx xxxx     ISUB_ACC = 10
0001 011x xxxx xxxx     IAND_ACC = 11
0001 100x xxxx xxxx     IOR_ACC = 12
0001 101x xxxx xxxx     IXOR_ACC = 13
0001 110x xxxx xxxx     ITAG_WITH = 14
0001 111x xxxx xxxx     INP_ABS = 15

/* instruction group 4 */
/* single variable instruction -- bit 11 is on */
/* instruction = (opcode >> 9) */

0000 100x xxxx xxxx     ISTORE_MEM = 4
0000 101x xxxx xxxx     INC_MEM = 5
0000 110x xxxx xxxx     IDEC_MEM = 6
0000 111x xxxx xxxx     INP_ABSQ = 7

/* instruction group 5 */
/* input relative instruction -- bit 10 is on */
/* instruction = (opcode >> 9) */

0000 010x xxxx xxxx     INP_REL = 2
0000 011x xxxx xxxx     INP_RELQ = 3

/* instruction group 6 */
/* single operand instruction -- bit 9 is on */
/* instruction = (opcode >> 6) */

0000 0010 00xx xxxx     IROT_LEFT = 8
0000 0010 01xx xxxx     IROT_RIGHT = 9
0000 0010 10xx xxxx     IEXT_BIT = 10
0000 0010 11xx xxxx     IPOS_ABS = 11
0000 0011 00xx xxxx     IPOS_REL = 12

/* instruction group 7 */
/* implied operand instruction - bits 15-5 off, bit 4 on */

0000 0000 0001 0000     INOP = 16
0000 0000 0001 0001     ICOMP_ACC = 17
0000 0000 0001 0010     ITWOCOMP_ACC = 18
0000 0000 0001 0011     IRETURN = 19
0000 0000 0001 0100     ION_TRACE = 20
0000 0000 0001 0101     IOFF_TRACE = 21
0000 0000 0001 0110     IABORT = 22
0000 0000 0001 0111     IFNOT_MAP = 23
0000 0000 0001 1000     IMARKLINE_O_NA = 24
0000 0000 0001 1001     IMARKLINE_S_NA = 25
0000 0000 0001 1010     IMARKLINE_O_A = 26
0000 0000 0001 1011     IMARKLINE_S_A = 27
0000 0000 0001 1100     IMARKSTATE_DISP = 28
0000 0000 0001 1101     IMARKSTATE_SUP = 29
0000 0000 0001 1110     INEWLINE = 30
0000 0000 0001 1111     IFETCH_POSITION = 31
« Last Edit: May 15, 2018, 07:19:22 pm by gslick »
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #11 on: May 15, 2018, 07:50:51 pm »
I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.
I think we're starting to find enough pieces.

The link to the manual that Tim posted above on the HP-UX Hosted Cross Assembler/Linker describes the format for relocatable files in Appendix D.  I haven't sat down to write a parser for it (yet), but the IA .R files appear to use at least some of the described record types.

I'm also looking at agIalEngine.cpp from the Analysis AddIn Wizard (which I think is where you got that snippet), and it looks like the parser might already be in there.  If I'm reading it right, "CagIalEngine::read_hdr()" starts right off with validating the "82 03" I found before.

agIalEngine.cpp appears to be a complete implementation of the IA interpreter.
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #12 on: May 15, 2018, 08:20:48 pm »
Yes, I extracted that opcode information from the agIalEngine.cpp file in the Analysis AddIn Wizard.

Comparing a listing file produced by running 10391B ASM.EXE on the sample I8085.S file against the a hex dump of the resulting I8085.R file I see some blocks that match between the two but also some extra bytes in the .R file between matching blocks that are not in the listing file. Maybe that has to do with the .R file being broken up into records, with a 128 word maximum per record, where the extra bytes in the .R file are part of the record structure wrapped around the raw instruction words.

I'll have to spend some time looking at the record structure documentation in 64851-97000_HP-UX_Cross-Assembler_Jun89.pdf and the record reading code in the agIalEngine.cpp file.

EDIT: Oh, I'm starting to see now that at least some of the extra bytes in the .R file that are not in the ASM.EXE output listing file are 0x5555 T-parameters before a set of 8 words in a double record, where the 0x5555 indicates that each of the following 8 words is two bytes absolute with no modifications.
« Last Edit: May 15, 2018, 10:56:26 pm by gslick »
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #13 on: May 16, 2018, 12:22:04 am »
Hmm, maybe I figured out what happens to a .R file during the IALDOWN transformation, which apparently occurs inside of the analyzer, not inside of the IALDOWN program itself.

It appears that first a 0x200-byte LIF header is inserted at the beginning of the file. Then a description header is inserted. I'm not sure if that is fixed or variable length. In the couple of files I looked at quickly it was 0x25 (37 decimal) bytes in length. Then the original .R file contents follow beginning with the 0x82 0x03 header bytes.

However, starting immediately after the initial 0x200-byte LIF header the remainder of the file is broken up into 0x00FE (254 decimal) byte length records, except for the final record of the file which may be shorter. Each record begins with the record length word inserted in MSB first order. After the final partial length record it appears that the file is padded out to a 0x100-byte boundary with essentially random data.

So it appears that an IA file that has gone through the IALDOWN transformation could be transformed back into an equivalent .R file by first deleting the 0x200-byte LIF header, then for each record delete the record length word at the beginning of the record, and for the final partial length record delete any extraneous data at the end of the record. Then go back and delete the description header at the beginning preceding the 0x82 0x03 header bytes.

I haven't verified that this is entirely correct yet. This is just from a quick look in a hex editor at a couple of IA files. I should try writing some code to do this reverse transformation process and run it on all of the IA files in the INVASM.ZIP collection, then run them through the IALDOWN process, and see if that results in identical IA files again.
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #14 on: May 16, 2018, 01:36:41 am »
Ah, very interesting.  I found this same structure of a record length of 0x00fe in the 16510 config files, including a short one at the end, all after the LIF header.

The C program I wrote in invasm_configtxt.zip already parses the 0x00fe records for the config files.  I don't know why I didn't think of looking for it in the IA files also.  It should be simple to modify it to handle the IA files.
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #15 on: May 16, 2018, 02:04:15 am »
If we can successfully transform IA files back into equivalent .R files then we should be able to use the 16900-series Analysis AddIn wizard tool to build those into .R files .DLL files to use on that platform. That would be nice. I wonder why Agilent / Keysight never bothered to provide such tools. Maybe they just thought the old IAs were obsolete enough they didn't think anyone would be interested in using them.

It would also be cool if we can write tools to based on the agIalEngine.cpp interpreter engine to disassemble the .R files back into something that can be assembled again to understand how some of the IAs work, and modify them for various reasons if desired.
 
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Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #16 on: May 16, 2018, 02:28:52 am »
Ok, attached is an extracted version of i6800_p as a test using a horribly hacked version of the configtxt tool.

It works for me.  I copied it onto my 16702B and used the IAL format utility on it.  It created the expected package in /logic/ia and I was able to load that into the Listing window, and this time *without* a segfault.  So, I think you figured it out!

Do you want to try it on your 16900?

I can polish up the extractor and convert the rest of them in the morning if you're successful.

And yes, I agree it would be great to be able to go all the way back to the .S so anyone can customize the IA as desired.
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #17 on: May 16, 2018, 02:42:19 am »
It might take me a while to get setup with the 16900 tools again. I think I had that on an 64-bit Windows 7 system where I installed an XP-mode VM so I could install Microsoft Visual Studio .NET 2003, which might not install or run correctly on Windows 7, or something like that. I might have pulled that drive out of that system. I'll have to see what I did with that. I'd rather not have to get all of the tools set up from scratch again.

OK, found the drive that I had set up with the 16900-series Analysis AddIn Tool wizard that I used to build a 16900-series version of the 10391B I8085 sample IA. I'll have to install that drive back in the system and see if I can get the tools running again and try building a 6800 IA.
« Last Edit: May 16, 2018, 02:52:02 am by gslick »
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #18 on: May 16, 2018, 06:27:21 pm »
One quick note about the 0x25 (37 decimal) byte IA file description header that follows the 0x200-byte LIF header at the beginning of an IA file. The IA file description header contains a 0x20 (32 decimal) length IA file description text field. The field is padded with space characters if necessary.

Immediately after the IA file description text field there is a single byte corresponding to the IALDOWN "Invasm" Field Options:
0xFF: A = No "Invasm" Field
0x00: B = "Invasm" Field with no pop-up
0x01: C = "Invasm" Field with pop-up. 2 choices in pop-up.
0x02: D = "Invasm" Field with pop-up. 8 choices in pop-up.

Field Option A means the IA should always have enough status information to be able to (re)synchronize which states are the beginning of instruction fetch cycles. The other Field Options mean the IA may need input from the user to indicate which states should be considered as the beginning of instruction fetch cycles. See Appendix B, Microprocessors with Incomplete Status, in the 10391B reference manual for more information.

For example in the case of the i6800_i IA the preprocessor interface has logic to provide extra status information and the Field Option is A, while the i6800_p IA for the general purpose probes does not have that status information and the Field Option is B.

For the IA files in the original INVASM.ZIP:
Code: [Select]
IA File: i68000_i
IA Description: "68000 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i68000_p
IA Description: "68000 IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i68008_i
IA Description: "68008 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i68008_p
IA Description: "68008 IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i6800_i
IA Description: "6800/02 IA FOR INTERFACE     1_0"
IA Field Option: A

IA File: i6800_p
IA Description: "6800/02 IA FOR GP PROBES     1_0"
IA Field Option: B

IA File: i68010_i
IA Description: "68010 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i68010_p
IA Description: "68010 IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i68020_i.p
IA Description: "68020 INVERSE ASSEMBLER      1_0"
IA Field Option: C

IA File: i6809e_p
IA Description: "6809E IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i6809_i
IA Description: "6809/9E IA FOR INTERFACE     1_0"
IA Field Option: A

IA File: i6809_p
IA Description: "6809 IA FOR GP PROBES        1_0"
IA Field Option: B

IA File: i80186e_.i
IA Description: "80186 ENHANCED IA            1_0"
IA Field Option: B

IA File: i80186_i
IA Description: "80186 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i80188e_.i
IA Description: "80188 ENHANCED IA            1_0"
IA Field Option: B

IA File: i80188_i
IA Description: "80188 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i80286_i
IA Description: "80286 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i80386_8.7
IA Description: "80386 IA WITH 80X87          1_0"
IA Field Option: D

IA File: i80386_i
IA Description: "80386 IA FOR INTERFACE       1_0"
IA Field Option: D

IA File: i8085_ip
IA Description: "8085 INVERSE ASSEMBLER       1_0"
IA Field Option: A

IA File: i8086_i
IA Description: "8086 IA FOR INTERFACE        1_0"
IA Field Option: B

IA File: i8088_i
IA Description: "8088 IA FOR INTERFACE        1_0"
IA Field Option: B

IA File: insc800_.i
IA Description: "NSC800 IA FOR INTERFACE      1_0"
IA Field Option: A

IA File: iz80_i
IA Description: "Z80 IA FOR INTERFACE         1_0"
IA Field Option: A
 
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Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #19 on: May 16, 2018, 10:10:32 pm »
I finished up the .R extractor and ran it on all the files in invasm.zip.  Attached is invasm_v3.zip which has the results as well as the previous output from configtxt.

As before, the source is included for reference.  (You can hate my pointer manipulation if it makes you feel better.  It is a one-time hack and not a good example.)

For each inverse assembler iXXX, there is now:

  iXXX.r - The extracted relocatable .R file.  Starts with .R magic 82 03.

  iXXX.info - The additional info in the header: The description and the Invasm Field Options (as per the previous post).

I'm posting this with the caveat that it's for testing since none of it, except for i6800_p.r, has been verified.

Any feedback welcome from anyone who wants to try loading the .r files via IALDOWN, IA Format, or any other utilities.
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #20 on: May 16, 2018, 11:59:01 pm »
I finished up the .R extractor and ran it on all the files in invasm.zip.  Attached is invasm_v3.zip which has the results as well as the previous output from configtxt.

I also started writing a file manipulation tool to help improve my own understanding of the file format and did my own version of a .R file from downloaded to analyzer format IA file extractor. I downloaded your invasm_v3.zip files and verified that all of the .R files I extracted binary compare with what you did. So that is a good checkpoint that we are in agreement there.

For the configuration text, have you looked at trying to decode the Master and Slave clock specifications, and the Normal, Demultiplex, or Mixed Clocks modes for each pod?

For 16510 modules the five J, K, L, M, and N clocks are available. Each of those 5 clocks can be specified as either Off, Negative Edge, Positive Edge, Either Edge, Qualifier Low, or Qualifier High, in any combination in a clock specification. The clocks are combined by OR'ing and AND'ing them. Clock edges are ORed to clock edges, clock qualifier levels are ORed to clock qualifier levels, and clock edges are ANDed to clock qualifier levels.

For example you could have (J↓ + K↑) • (M=1 + N=0) as a clock specification.

If all of the pods are clocked in Normal mode then only the Master clock specification applies. If any pods are clocked in either Demultiplex or Mixed Clocks modes then the Slave clock specification also applies.

As far as I know the 16510 Demultiplex and Mixed Clocks modes which split a 16 channel pod into two 8 channel halves are not implemented in the same way in any of the state modules newer than the 16510. In any newer state modules an entire pod is either Master or Slave clocked, or in Demultiplex mode a pod is both Master and Slave clocked but then the other pod in the pod pair becomes unavailable. These differences are probably why a mainframe will not load 16510 configuration files in newer state modules when there is no direct mapping between the 16510 and newer state modules in some configurations.

For example, can you extract the clock specifications and pod clock modes from the c8085_i file?

Code: [Select]
Title: 8085 CONFIG FOR INTERFACE    1_0

Pod assigments (? = disabled)
-----------------------------
Label  0: ADDR     (16 bits):  A2: ******** ******** 
Label  1: DATA     ( 8 bits):  A1: ........ ******** 
Label  2: STAT     ( 4 bits):  A1: ....**** ........
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #21 on: May 18, 2018, 04:26:44 am »
I made some progress in trying to understand the implementation details of an assembled IAL .R binary file.

I hacked up some proof of concept Python code that can read a .R binary file and parse it into the three binary segments, the Program, Data, and Common segments. The segment names are misleading. The Program segment is where the IAL system variables and user defined variables are located. The Common segment is where strings and output format specifications are located, and the Data segment is where instruction opcodes are located.

Using only the I8085.S sample from the 10391B kit for testing so far it appears that the data that is being populated into the three segments from parsing the assembled I8085.R binary file matches the binary data that is shown in the listing file.

The next step would be to try to hack up some proof of concept code than can unassemble the instruction opcodes in the Data segment and try to produce a functionally equivalent .S source file, which would also include declarations of the variables in the Program segment and the strings in the Common segment, and corresponding references to those variables and strings as instruction operands.

It might take a bit more time working my way through the agIalEngine.cpp code to completely understand all of the details of instruction opcode decoding than it did to get my current understanding of the .R binary file segment and relocation data details. But it does look promising now that this is doable.
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #22 on: May 20, 2018, 08:23:19 pm »
...
For the configuration text, have you looked at trying to decode the Master and Slave clock specifications, and the Normal, Demultiplex, or Mixed Clocks modes for each pod?
...
I looked at this with your posting and the user manual in hand.  Unfortunately, it's not immediately obvious where the clocking information lies or how it's encoded in the configuration file.

I think the only way to accomplish this is to actually have a 16510, change one clocking choice at a time, and then observe the resulting change in the saved configuration file.

If we limit the set of relevant clocking configurations to only the ones that are in invasm.zip, it would probably be a lot faster to manually transcribe them by looking at the screen, or from a screen capture.

I think familiarity with a specific processor can also quickly lead a user to the correct clocking configuration to derive the DATA, ADDR, and STAT labels.

For the 8085 specifically, one glance at the datasheet shows that it requires demultiplexing to create the separate fields for DATA and ADDR.  ALE would be the slave clock for demultiplexing.  Looking at the timing diagram and the breakout of the STAT bits show that we need to be able to clock the master on RD, WR, and the special case of INTA.

Knowing the 16510 configuration can help, say if there's complicated qualifiers and OR'd clocks, but in some cases the configuration may not be directly translatable anyway due to the differences in the way the 16510 does it, as you point out.

I guess I'm not convinced that it's going to be worth the investment in time to figure out and write a generalized clocking decoder for the 16510.  I would, however, pony up time to manually transcribe the clock settings for all of the IA configurations in invasm.zip, if you or someone were to provide the screen captures from a 16510.

Or maybe skip the transcribing step completely, and provide complete captures of the configurations and be done with it.  (Which kind-of obviates the work I already did on the config decoder, but that's ok.)
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #23 on: May 22, 2018, 02:04:19 pm »
Just wanted to point out that the IA files compatible with 1650/16500 are also compatible with 1660/1670 series, maybe the top post should reflect that.
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #24 on: May 22, 2018, 08:13:17 pm »
I'm making some progress in being able to decode an IAL style inverse assembler back into equivalent source code that could be assembled with the 10391B ASM.EXE assembler.

Below is what I currently get from processing the "6800/02 IA FOR GP PROBES     1_0" inverse assembler file  i6800_p. I still need to handle declaring variables and constants with their initial values, and declaring strings and format strings instead of putting them inline.

Interesting that it turns out that the "6800/02 IA FOR GP PROBES     1_0" inverse assembler file  i6800_p is the same as the "6800/02 IA FOR INTERFACE     1_0" inverse assembler file  i6800_i file, except that the i6800_p version does this, which selects which status decoding is used (except in the TASK = 3 case):

Code: [Select]
LABEL_0015
    GOTO LABEL_0016


while the i6800_i version does this:

Code: [Select]
LABEL_0015
    GOTO LABEL_0026


Code: [Select]
"IAL"

    IF TASK = 3 THEN GOTO LABEL_0010
    IF TASK = 4 THEN GOTO LABEL_0015
    IF TASK = 5 THEN GOTO LABEL_0015
    OUTPUT "Illegal Task Request"
    ABORT
    OUTPUT "Data Error"
    ABORT

LABEL_000D
    POSITION ABS,1
    OUTPUT "Illegal Opcode"
    ABORT

LABEL_0010
    LOAD ID_CODE
    IF 7,0 = VAR_0048 THEN GOTO LABEL_0016
    GOTO LABEL_0026

LABEL_0015
    GOTO LABEL_0016

LABEL_0016
    LOAD INPUT_TAG
    IF 17,16 = 0 THEN GOTO LABEL_0043
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_0043
    LOAD INPUT_TAG
    CASE_OF 1,0
        GOTO LABEL_01A2
        GOTO LABEL_0043
        GOTO LABEL_0054
        NOP
    CASE_END
    RETURN

LABEL_0026
    LOAD INPUT_STATUS
    IF 3,0 = 9 THEN GOTO LABEL_005B
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 3,0
        OUTPUT "Illegal Opcode"
        OUTPUT "operand fetch"
        OUTPUT "stack read"
        OUTPUT "stack write"
        OUTPUT "stack read"
        OUTPUT "stack write"
        OUTPUT "halt"
        OUTPUT "vector"
        OUTPUT "unused"
        OUTPUT "opcode fetch"
        OUTPUT "DMA read"
        OUTPUT "DMA write"
        OUTPUT "memory write"
        OUTPUT "memory read"
        OUTPUT "out of synch"
        OUTPUT "interrupt ack"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0043
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 2,0
        OUTPUT "non valid cycle"
        OUTPUT "non valid cycle"
        OUTPUT "memory write"
        OUTPUT "memory read"
        OUTPUT "dma or halt"
        OUTPUT "dma or halt"
        OUTPUT "dma or halt"
        OUTPUT "dma or halt"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0054
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    POSITION REL,1
    OUTPUT "unused cycle"
    SET RETURN_FLAGS,0
    RETURN

LABEL_005B
    SET RETURN_FLAGS,1
    INPUT REL,0
    LOAD INITIAL_DATA
    CASE_OF 7,7
        GOTO LABEL_0062
        GOTO LABEL_0103
    CASE_END

LABEL_0062
    CASE_OF 7,4
        GOTO LABEL_006C
        GOTO LABEL_008C
        GOTO LABEL_009F
        GOTO LABEL_00C4
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
    CASE_END

LABEL_006C
    CASE_OF 3,0
        GOTO LABEL_000D
        OUTPUT "NOP"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAP"
        OUTPUT "TPA"
        OUTPUT "INX"
        OUTPUT "DEX"
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
    CASE_END
    RETURN

LABEL_007F
    OUTPUT "CL"
    GOTO LABEL_0082

LABEL_0081
    OUTPUT "SE"

LABEL_0082
    IF 2,1 = 1 THEN OUTPUT "V"
    IF 2,1 = 2 THEN OUTPUT "C"
    IF 2,1 = 3 THEN OUTPUT "I"
    RETURN

LABEL_008C
    CASE_OF 3,0
        OUTPUT "SBA"
        OUTPUT "CBA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAB"
        OUTPUT "TBA"
        GOTO LABEL_000D
        OUTPUT "DAA"
        GOTO LABEL_000D
        OUTPUT "ABA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
    CASE_END
    RETURN

LABEL_009F
    OUTPUT "B"
    CASE_OF 3,0
        OUTPUT "RA"
        GOTO LABEL_000D
        OUTPUT "HI"
        OUTPUT "LS"
        OUTPUT "CC"
        OUTPUT "CS"
        OUTPUT "NE"
        OUTPUT "EQ"
        OUTPUT "VC"
        OUTPUT "VS"
        OUTPUT "PL"
        OUTPUT "MI"
        OUTPUT "GE"
        OUTPUT "LT"
        OUTPUT "GT"
        OUTPUT "LE"
    CASE_END

LABEL_00B2
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    ADD 1
    STORE VAR_003E
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    POSITION ABS,6
    IF 7,7 = 1 THEN INCLUSIVE_OR VAR_0046
    ADD VAR_003E
    AND VAR_0042
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_00C4
    CASE_OF 3,0
        OUTPUT "TSX"
        OUTPUT "INS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        OUTPUT "DES"
        OUTPUT "TXS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        GOTO LABEL_000D
        OUTPUT "RTS"
        GOTO LABEL_000D
        OUTPUT "RTI"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "WAI"
        OUTPUT "SWI"
    CASE_END
    RETURN

LABEL_00D7
    IF 2,2 = 0 THEN OUTPUT "PUL"
    IF 2,2 = 1 THEN OUTPUT "PSH"
    CASE_OF 0,0
        GOTO LABEL_00FF
        GOTO LABEL_0101
    CASE_END
    RETURN

LABEL_00E2
    CASE_OF 3,0
        OUTPUT "NEG"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "COM"
        OUTPUT "LSR"
        GOTO LABEL_000D
        OUTPUT "ROR"
        OUTPUT "ASR"
        OUTPUT "ASL"
        OUTPUT "ROL"
        OUTPUT "DEC"
        GOTO LABEL_000D
        OUTPUT "INC"
        OUTPUT "TST"
        GOTO LABEL_00F5
        OUTPUT "CLR"
    CASE_END
    GOTO LABEL_00F9

LABEL_00F5
    CASE_OF 5,5
        GOTO LABEL_000D
        OUTPUT "JMP"
    CASE_END

LABEL_00F9
    CASE_OF 5,4
        GOTO LABEL_00FF
        GOTO LABEL_0101
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_00FF
    OUTPUT "A"
    RETURN

LABEL_0101
    OUTPUT "B"
    RETURN

LABEL_0103
    CASE_OF 3,0
        OUTPUT "SUB"
        OUTPUT "CMP"
        OUTPUT "SBC"
        GOTO LABEL_000D
        OUTPUT "AND"
        OUTPUT "BIT"
        OUTPUT "LDA"
        GOTO LABEL_0116
        OUTPUT "EOR"
        OUTPUT "ADC"
        OUTPUT "ORA"
        OUTPUT "ADD"
        GOTO LABEL_011E
        GOTO LABEL_0126
        GOTO LABEL_0138
        GOTO LABEL_0141
    CASE_END
    GOTO LABEL_0150

LABEL_0116
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "STA"
    GOTO LABEL_0150

LABEL_011E
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    OUTPUT "CPX"
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0126
    IF 7,4 = 9 THEN GOTO LABEL_000D
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    IF 5,4 = 0 THEN GOTO LABEL_0136
    OUTPUT "JSR"
    IF 5,4 = 2 THEN GOTO LABEL_016B
    IF 5,4 = 3 THEN GOTO LABEL_0170

LABEL_0136
    OUTPUT "BSR"
    GOTO LABEL_00B2

LABEL_0138
    OUTPUT "LD"
    CASE_OF 6,6
        OUTPUT "S"
        OUTPUT "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0141
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "ST"
    CASE_OF 6,6
        OUTPUT "S"
        OUTPUT "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0150
    IF 6,6 = 0 THEN CALL LABEL_00FF
    IF 6,6 = 1 THEN CALL LABEL_0101

LABEL_0156
    CASE_OF 5,4
        GOTO LABEL_015C
        GOTO LABEL_0166
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_015C
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    RETURN

LABEL_0161
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_017E
    OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_0166
    POSITION ABS,6
    CALL LABEL_0175
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_016B
    POSITION ABS,6
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    OUTPUT ",X"
    RETURN

LABEL_0170
    POSITION ABS,6
    CALL LABEL_017E
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_0175
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    RETURN

LABEL_017C
    OUTPUT "**"
    ABORT

LABEL_017E
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    STORE VAR_003C
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_0192
    LOAD INPUT_DATA
    ROTATE LEFT,8
    AND VAR_0044
    STORE VAR_0034
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_019D
    LOAD INPUT_DATA
    AND VAR_004A
    INCLUSIVE_OR VAR_0034
    RETURN

LABEL_0192
    OUTPUT "**"
    LOAD VAR_003C
    STORE INPUT_ADDRESS
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_01A0
    LOAD INPUT_DATA
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    ABORT

LABEL_019D
    LOAD VAR_0034
    ROTATE RIGHT,8
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2

LABEL_01A0
    OUTPUT "**"
    ABORT

LABEL_01A2
    SET VAR_0040,0

LABEL_01A3
    LOAD INPUT_STATUS
    IF 1,0 = 3 THEN GOTO LABEL_01AE
    TAG_WITH 2
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    GOTO LABEL_01A3

LABEL_01AE
    LOAD INPUT_DATA
    CASE_OF 7,0
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD VAR_004C
        LOAD VAR_004E
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0050
        GOTO LABEL_000D
        LOAD VAR_0052
        LOAD VAR_0054
        LOAD VAR_0056
        LOAD VAR_0058
        LOAD VAR_005A
        LOAD VAR_005C
        LOAD VAR_005E
        LOAD VAR_0060
        LOAD VAR_0062
        LOAD VAR_0064
        LOAD VAR_0066
        LOAD VAR_0068
        LOAD VAR_006A
        LOAD VAR_006C
        LOAD VAR_006E
        LOAD VAR_0070
        LOAD VAR_0072
        LOAD VAR_0074
        LOAD VAR_0076
        LOAD VAR_0078
        LOAD VAR_007A
        LOAD VAR_007C
        GOTO LABEL_000D
        LOAD VAR_007E
        GOTO LABEL_000D
        LOAD VAR_0080
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0082
        LOAD VAR_0084
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD VAR_0086
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0088
        LOAD VAR_008A
        GOTO LABEL_000D
        LOAD VAR_008C
        LOAD VAR_008E
        LOAD VAR_0090
        LOAD VAR_0092
        LOAD VAR_0094
        GOTO LABEL_000D
        LOAD VAR_0096
        LOAD VAR_0098
        LOAD VAR_009A
        LOAD VAR_009C
        LOAD VAR_009E
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_00A0
        LOAD VAR_00A2
        GOTO LABEL_000D
        LOAD VAR_00A4
        LOAD VAR_00A6
        LOAD VAR_00A8
        LOAD VAR_00AA
        LOAD VAR_00AC
        GOTO LABEL_000D
        LOAD VAR_00AE
        LOAD VAR_00B0
        LOAD VAR_00B2
        LOAD VAR_00B4
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD VAR_00B6
        LOAD VAR_00B8
        LOAD VAR_00BA
        GOTO LABEL_000D
        LOAD VAR_00BC
        LOAD VAR_00BE
        LOAD VAR_00C0
        GOTO LABEL_000D
        LOAD VAR_00C2
        LOAD VAR_00C4
        LOAD VAR_00C6
        LOAD VAR_00C8
        LOAD VAR_00CA
        LOAD VAR_00CC
        LOAD VAR_00CE
        LOAD VAR_00D0
        LOAD VAR_00D2
        GOTO LABEL_000D
        LOAD VAR_00D4
        LOAD VAR_00D6
        LOAD VAR_00D8
        LOAD VAR_00DA
        LOAD VAR_00DC
        GOTO LABEL_000D
        LOAD VAR_00DE
        LOAD VAR_00E0
        LOAD VAR_00E2
        LOAD VAR_00E4
        LOAD VAR_00E6
        LOAD VAR_00E8
        LOAD VAR_00EA
        LOAD VAR_00EC
        LOAD VAR_00EE
        LOAD VAR_00F0
        LOAD VAR_00F2
        LOAD VAR_00F4
        LOAD VAR_00F6
        LOAD VAR_00F8
        LOAD VAR_00FA
        GOTO LABEL_000D
        LOAD VAR_00FC
        LOAD VAR_00FE
        LOAD VAR_0100
        LOAD VAR_0102
        LOAD VAR_0104
        LOAD VAR_0106
        LOAD VAR_0108
        LOAD VAR_010A
        LOAD VAR_010C
        LOAD VAR_010E
        LOAD VAR_0110
        LOAD VAR_0112
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0114
        GOTO LABEL_000D
        LOAD VAR_0116
        LOAD VAR_0118
        LOAD VAR_011A
        GOTO LABEL_000D
        LOAD VAR_011C
        LOAD VAR_011E
        LOAD VAR_0120
        LOAD VAR_0122
        LOAD VAR_0124
        LOAD VAR_0126
        LOAD VAR_0128
        LOAD VAR_012A
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_012C
        LOAD VAR_012E
        LOAD VAR_0130
        LOAD VAR_0132
        LOAD VAR_0134
        GOTO LABEL_000D
        LOAD VAR_0136
        LOAD VAR_0138
        LOAD VAR_013A
        LOAD VAR_013C
        LOAD VAR_013E
        LOAD VAR_0140
        LOAD VAR_0142
        LOAD VAR_0144
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0146
        LOAD VAR_0148
        LOAD VAR_014A
        LOAD VAR_014C
        LOAD VAR_014E
        GOTO LABEL_000D
        LOAD VAR_0150
        LOAD VAR_0152
        LOAD VAR_0154
        LOAD VAR_0156
        LOAD VAR_0158
        LOAD VAR_015A
        LOAD VAR_015C
        LOAD VAR_015E
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0160
        LOAD VAR_0162
    CASE_END

LABEL_02B1
    STORE VAR_0036
    AND 3
    STORE VAR_003A
    IF 1,0 = 3 THEN GOTO LABEL_005B
    TAG_WITH VAR_003A

LABEL_02B8
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_02B8
    LOAD VAR_0036
    ROTATE RIGHT,2
    GOTO LABEL_02B1
 
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Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #25 on: May 23, 2018, 02:25:28 pm »
That's some great progress, gslick!

Interesting that TASK==3 (for the HP 64620) could dynamically select which STAT decoding to use.  It seems like that functionality would be easy to carry forward to newer models instead of having to load separate IAs.  It's not like they were saving any IA interpreter code space.
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #26 on: May 25, 2018, 05:59:32 am »
Below is what I now get from processing the "6800/02 IA FOR GP PROBES     1_0" inverse assembler file i6800_p after adding some logic to handle declaring variables and constants with their initial values, and declaring strings and format strings instead of putting them inline.

If you assemble this with the 10391B ASM.EXE assembler it should produce an i6800_p.r relocatable file that binary compares with the one extracted from the INVASM.ZIP collection, with the exception of the Name Record at the beginning of the file which includes the complete source file name and path. If the file name path length differs the whole remainder of the .R file will shift. There is also some other descriptive information in the Name Record which might get populated differently between the 10391B ASM.EXE assembler and HP tools that might have been used on different hosts.

The .R decoding code I wrote to do this is rather ugly. I just wanted to try to figure out exactly what it needed to do. I should make sure it works correctly on the other IA .R files, and then try to clean up the code.

Code: [Select]
"IAL"

*
* Original Source File Name: d:\ial\procs\i6800_p.s
*

        LABEL_TITLE      " 6800/6802 Mnemonic"
        BASE_TITLE       "        hex"
        SEARCH_LIMIT     12
        DEFAULT_WIDTH    21
        MAPPED_WIDTH     21
VAR_0034        VARIABLE 000000000H
VAR_0036        VARIABLE 000000000H
VAR_0038        VARIABLE 000000000H    * unreferenced
VAR_003A        VARIABLE 000000000H
VAR_003C        VARIABLE 000000000H
VAR_003E        VARIABLE 000000000H
VAR_0040        VARIABLE 000000000H
FMT_0010        FORMAT 16,HEX,4
FMT_0012        FORMAT 8,HEX,2
STR_0014        ASCII "A"
STR_0015        ASCII "B"
STR_0016        ASCII "C"
STR_0017        ASCII "H"    * unreferenced
STR_0018        ASCII "I"
STR_0019        ASCII "S"
STR_001A        ASCII "V"
STR_001B        ASCII "X"
STR_001C        ASCII "PUL"
STR_001E        ASCII "PSH"
STR_0020        ASCII ","    * unreferenced
STR_0021        ASCII "-"    * unreferenced
STR_0022        ASCII ",X"
STR_0024        ASCII "operand fetch"
STR_002B        ASCII "stack read"
STR_0031        ASCII "stack write"
STR_0037        ASCII "halt"
STR_003A        ASCII "vector"
STR_003E        ASCII "unused"
STR_0042        ASCII "opcode fetch"
STR_0049        ASCII "DMA read"
STR_004E        ASCII "DMA write"
STR_0053        ASCII "memory read"
STR_0059        ASCII "memory write"
STR_0060        ASCII "out of synch"
STR_0067        ASCII "interrupt ack"
STR_006E        ASCII "Illegal Opcode"
STR_0076        ASCII "unused cycle"
STR_007D        ASCII "dma or halt"
STR_0083        ASCII "non valid cycle"
CONST_0042      CONSTANT 00000FFFFH
CONST_0044      CONSTANT 00000FF00H
CONST_0046      CONSTANT 0FFFFFF00H

ENTRY_POINT
    IF TASK = 3 THEN GOTO LABEL_0010
    IF TASK = 4 THEN GOTO LABEL_0015
    IF TASK = 5 THEN GOTO LABEL_0015
    OUTPUT "Illegal Task Request"
    ABORT
    OUTPUT "Data Error"
    ABORT

LABEL_000D
    POSITION ABS,1
    OUTPUT STR_006E    * "Illegal Opcode"
    ABORT

LABEL_0010
    LOAD ID_CODE
    IF 7,0 = 0000000F0H THEN GOTO LABEL_0016
    GOTO LABEL_0026

LABEL_0015
    GOTO LABEL_0016

LABEL_0016
    LOAD INPUT_TAG
    IF 17,16 = 0 THEN GOTO LABEL_0043
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_0043
    LOAD INPUT_TAG
    CASE_OF 1,0
        GOTO LABEL_01A2
        GOTO LABEL_0043
        GOTO LABEL_0054
        NOP
    CASE_END
    RETURN

LABEL_0026
    LOAD INPUT_STATUS
    IF 3,0 = 9 THEN GOTO LABEL_005B
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FMT_0012
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 3,0
        OUTPUT STR_006E    * "Illegal Opcode"
        OUTPUT STR_0024    * "operand fetch"
        OUTPUT STR_002B    * "stack read"
        OUTPUT STR_0031    * "stack write"
        OUTPUT STR_002B    * "stack read"
        OUTPUT STR_0031    * "stack write"
        OUTPUT STR_0037    * "halt"
        OUTPUT STR_003A    * "vector"
        OUTPUT STR_003E    * "unused"
        OUTPUT STR_0042    * "opcode fetch"
        OUTPUT STR_0049    * "DMA read"
        OUTPUT STR_004E    * "DMA write"
        OUTPUT STR_0059    * "memory write"
        OUTPUT STR_0053    * "memory read"
        OUTPUT STR_0060    * "out of synch"
        OUTPUT STR_0067    * "interrupt ack"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0043
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FMT_0012
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 2,0
        OUTPUT STR_0083    * "non valid cycle"
        OUTPUT STR_0083    * "non valid cycle"
        OUTPUT STR_0059    * "memory write"
        OUTPUT STR_0053    * "memory read"
        OUTPUT STR_007D    * "dma or halt"
        OUTPUT STR_007D    * "dma or halt"
        OUTPUT STR_007D    * "dma or halt"
        OUTPUT STR_007D    * "dma or halt"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0054
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FMT_0012
    POSITION REL,1
    OUTPUT STR_0076    * "unused cycle"
    SET RETURN_FLAGS,0
    RETURN

LABEL_005B
    SET RETURN_FLAGS,1
    INPUT REL,0
    LOAD INITIAL_DATA
    CASE_OF 7,7
        GOTO LABEL_0062
        GOTO LABEL_0103
    CASE_END

LABEL_0062
    CASE_OF 7,4
        GOTO LABEL_006C
        GOTO LABEL_008C
        GOTO LABEL_009F
        GOTO LABEL_00C4
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
    CASE_END

LABEL_006C
    CASE_OF 3,0
        GOTO LABEL_000D
        OUTPUT "NOP"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAP"
        OUTPUT "TPA"
        OUTPUT "INX"
        OUTPUT "DEX"
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
    CASE_END
    RETURN

LABEL_007F
    OUTPUT "CL"
    GOTO LABEL_0082

LABEL_0081
    OUTPUT "SE"

LABEL_0082
    IF 2,1 = 1 THEN OUTPUT STR_001A    * "V"
    IF 2,1 = 2 THEN OUTPUT STR_0016    * "C"
    IF 2,1 = 3 THEN OUTPUT STR_0018    * "I"
    RETURN

LABEL_008C
    CASE_OF 3,0
        OUTPUT "SBA"
        OUTPUT "CBA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAB"
        OUTPUT "TBA"
        GOTO LABEL_000D
        OUTPUT "DAA"
        GOTO LABEL_000D
        OUTPUT "ABA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
    CASE_END
    RETURN

LABEL_009F
    OUTPUT STR_0015    * "B"
    CASE_OF 3,0
        OUTPUT "RA"
        GOTO LABEL_000D
        OUTPUT "HI"
        OUTPUT "LS"
        OUTPUT "CC"
        OUTPUT "CS"
        OUTPUT "NE"
        OUTPUT "EQ"
        OUTPUT "VC"
        OUTPUT "VS"
        OUTPUT "PL"
        OUTPUT "MI"
        OUTPUT "GE"
        OUTPUT "LT"
        OUTPUT "GT"
        OUTPUT "LE"
    CASE_END

LABEL_00B2
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    ADD 1
    STORE VAR_003E
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    POSITION ABS,6
    IF 7,7 = 1 THEN INCLUSIVE_OR CONST_0046
    ADD VAR_003E
    AND CONST_0042
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_00C4
    CASE_OF 3,0
        OUTPUT "TSX"
        OUTPUT "INS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        OUTPUT "DES"
        OUTPUT "TXS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        GOTO LABEL_000D
        OUTPUT "RTS"
        GOTO LABEL_000D
        OUTPUT "RTI"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "WAI"
        OUTPUT "SWI"
    CASE_END
    RETURN

LABEL_00D7
    IF 2,2 = 0 THEN OUTPUT STR_001C    * "PUL"
    IF 2,2 = 1 THEN OUTPUT STR_001E    * "PSH"
    CASE_OF 0,0
        GOTO LABEL_00FF
        GOTO LABEL_0101
    CASE_END
    RETURN

LABEL_00E2
    CASE_OF 3,0
        OUTPUT "NEG"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "COM"
        OUTPUT "LSR"
        GOTO LABEL_000D
        OUTPUT "ROR"
        OUTPUT "ASR"
        OUTPUT "ASL"
        OUTPUT "ROL"
        OUTPUT "DEC"
        GOTO LABEL_000D
        OUTPUT "INC"
        OUTPUT "TST"
        GOTO LABEL_00F5
        OUTPUT "CLR"
    CASE_END
    GOTO LABEL_00F9

LABEL_00F5
    CASE_OF 5,5
        GOTO LABEL_000D
        OUTPUT "JMP"
    CASE_END

LABEL_00F9
    CASE_OF 5,4
        GOTO LABEL_00FF
        GOTO LABEL_0101
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_00FF
    OUTPUT STR_0014    * "A"
    RETURN

LABEL_0101
    OUTPUT STR_0015    * "B"
    RETURN

LABEL_0103
    CASE_OF 3,0
        OUTPUT "SUB"
        OUTPUT "CMP"
        OUTPUT "SBC"
        GOTO LABEL_000D
        OUTPUT "AND"
        OUTPUT "BIT"
        OUTPUT "LDA"
        GOTO LABEL_0116
        OUTPUT "EOR"
        OUTPUT "ADC"
        OUTPUT "ORA"
        OUTPUT "ADD"
        GOTO LABEL_011E
        GOTO LABEL_0126
        GOTO LABEL_0138
        GOTO LABEL_0141
    CASE_END
    GOTO LABEL_0150

LABEL_0116
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "STA"
    GOTO LABEL_0150

LABEL_011E
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    OUTPUT "CPX"
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0126
    IF 7,4 = 9 THEN GOTO LABEL_000D
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    IF 5,4 = 0 THEN GOTO LABEL_0136
    OUTPUT "JSR"
    IF 5,4 = 2 THEN GOTO LABEL_016B
    IF 5,4 = 3 THEN GOTO LABEL_0170

LABEL_0136
    OUTPUT "BSR"
    GOTO LABEL_00B2

LABEL_0138
    OUTPUT "LD"
    CASE_OF 6,6
        OUTPUT STR_0019    * "S"
        OUTPUT STR_001B    * "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0141
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "ST"
    CASE_OF 6,6
        OUTPUT STR_0019    * "S"
        OUTPUT STR_001B    * "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0150
    IF 6,6 = 0 THEN CALL LABEL_00FF
    IF 6,6 = 1 THEN CALL LABEL_0101

LABEL_0156
    CASE_OF 5,4
        GOTO LABEL_015C
        GOTO LABEL_0166
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_015C
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FMT_0012
    RETURN

LABEL_0161
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_017E
    OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_0166
    POSITION ABS,6
    CALL LABEL_0175
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_016B
    POSITION ABS,6
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FMT_0012
    OUTPUT STR_0022    * ",X"
    RETURN

LABEL_0170
    POSITION ABS,6
    CALL LABEL_017E
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_0175
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    RETURN

LABEL_017C
    OUTPUT "**"
    ABORT

LABEL_017E
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    STORE VAR_003C
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_0192
    LOAD INPUT_DATA
    ROTATE LEFT,8
    AND CONST_0044
    STORE VAR_0034
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_019D
    LOAD INPUT_DATA
    AND 0000000FFH
    INCLUSIVE_OR VAR_0034
    RETURN

LABEL_0192
    OUTPUT "**"
    LOAD VAR_003C
    STORE INPUT_ADDRESS
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_01A0
    LOAD INPUT_DATA
    OUTPUT ACCUMULATOR,FMT_0012
    ABORT

LABEL_019D
    LOAD VAR_0034
    ROTATE RIGHT,8
    OUTPUT ACCUMULATOR,FMT_0012

LABEL_01A0
    OUTPUT "**"
    ABORT

LABEL_01A2
    SET VAR_0040,0

LABEL_01A3
    LOAD INPUT_STATUS
    IF 1,0 = 3 THEN GOTO LABEL_01AE
    TAG_WITH 2
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    GOTO LABEL_01A3

LABEL_01AE
    LOAD INPUT_DATA
    CASE_OF 7,0
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 0000003A8H
        LOAD 0000003A8H
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 0000003A4H
        GOTO LABEL_000D
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A8H
        LOAD 0000003A8H
        LOAD 000000368H
        LOAD 000000368H
        LOAD 0000003A8H
        LOAD 0000003A8H
        LOAD 000000398H
        LOAD 000000398H
        GOTO LABEL_000D
        LOAD 000000D68H
        GOTO LABEL_000D
        LOAD 000355568H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 00D695558H
        LOAD 003595558H
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 00000D9A4H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        GOTO LABEL_000D
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        GOTO LABEL_000D
        LOAD 00000D9A4H
        LOAD 00000EAA4H
        LOAD 0000003A4H
        LOAD 00000D9A4H
        LOAD 000003654H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 000003654H
        LOAD 000003654H
        GOTO LABEL_000D
        LOAD 000003654H
        LOAD 000003654H
        LOAD 000003654H
        LOAD 000003654H
        LOAD 000003654H
        GOTO LABEL_000D
        LOAD 000003654H
        LOAD 000003A54H
        LOAD 0000000D4H
        LOAD 000003654H
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 0000000D4H
        LOAD 00003A964H
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 000000364H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 000000354H
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000D64H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        GOTO LABEL_000D
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 0000036A4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 0000035A4H
        LOAD 00003A964H
        LOAD 0000035A4H
        LOAD 00000D6A4H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000D94H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000D54H
        LOAD 0000EA594H
        LOAD 000000D54H
        LOAD 000003594H
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 000000364H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000D64H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        GOTO LABEL_000D
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 0000036A4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 0000035A4H
        LOAD 00000D6A4H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000D94H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 000000D54H
        LOAD 000003594H
    CASE_END

LABEL_02B1
    STORE VAR_0036
    AND 3
    STORE VAR_003A
    IF 1,0 = 3 THEN GOTO LABEL_005B
    TAG_WITH VAR_003A

LABEL_02B8
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_02B8
    LOAD VAR_0036
    ROTATE RIGHT,2
    GOTO LABEL_02B1
 
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Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #27 on: May 25, 2018, 02:35:02 pm »
Wow, this is great!

As a double check I changed some of the state decode text slightly, recompiled with ASM.EXE, and loaded the new version with the IA Format Utility on a 16702B.  Works perfectly on a 6802 processor I have connected.

I like your automatic comments for "unreferenced" and carrying the text values back to the line(s) that references it.  Your "unreferenced" works better than the -x (cross-reference) option in ASM.EXE.  The -x option misses references inside IF statements.

One thing I wanted to do with the 6800 IA is remove the dependency for displaying VMA=0 (unused) memory cycles.  When looking at code flow, I don't really care about internal processor cycles that only clutter up the screen and waste capture memory.  Some of the other display states not currently available via general probing can also be added.  Now it's all possible without starting from scratch.
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #28 on: May 26, 2018, 05:36:58 pm »
I went through all 24 of the .R files extracted from the Inverse Assembler files in the original INVASM.ZIP and decoded them back into .S source files for use with the 10391B ASM.EXE assembler.

When the exception of the differences in original source file name information in the initial Name Record the resulting .R files produced by assembling the .S source files for use with the 10391B ASM.EXE assembler should binary compare with the originally extracted .R files.

The only other exception is that both the i80386_i.R and i80386_8.7.R files contains records for what appears to be a format string with the value 0x4401FFFF, which might mean "FORMAT 32,HEX,LEFT_JUSTIFIED", which should normally have a value 0x240883E0 without any of the extra bits set. Maybe the value 0x4401FFFF means something else. In both cases they appears to be unreferenced.

EDIT: I figured this out. The special format value 0x4401FFFF means "FORMAT ASCII". I missed that FORMAT option in the 10391B manual. I'll have to go back later and update the generated .S files where that was decoded as "FORMAT 32,HEX,LEFT_JUSTIFIED".

One of the last things that I had to figure out was the correct syntax for these opcodes. They are not listed in the 10391B manual, but are present in the AIAL table file. Three of the files in the INVASM collection use MARK_LINE opcodes.

Code: [Select]
                        1 "IAL"
                        2
    0000                3 ENTRY_POINT
    0000 00000000       4     NOP
    0001 0014           5     TRACE_ON                    * ION_TRACE = 20
    0002 0015           6     TRACE_OFF                   * IOFF_TRACE = 21
    0003 0018           7     MARK_LINE OTHER,NO_ADDRESS  * IMARKLINE_O_NA = 24
    0004 0019           8     MARK_LINE SOURCE,NO_ADDRESS * IMARKLINE_S_NA = 25
    0005 001A           9     MARK_LINE OTHER             * IMARKLINE_O_A = 26
    0006 001B          10     MARK_LINE SOURCE            * IMARKLINE_S_A = 27
    0007 001C          11     MARK_STATE DISPLAYED        * IMARKSTATE_DISP = 28
    0008 001D          12     MARK_STATE SUPPRESSED       * IMARKSTATE_SUP = 29
    0009 0013          13     RETURN

I haven't taken a real close look at these generated .S source files to make sure everything looks reasonable in all of them. I was more focused on just making sure they all assemble correctly and regenerate matching .R files for now. I'll go ahead and share what I have so far, for the handful of people that might actually be interested in this stuff.
« Last Edit: May 26, 2018, 08:26:16 pm by gslick »
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #29 on: May 26, 2018, 08:54:57 pm »
Attached are decoded Inverse Assembler .S source code files for the 10342B HPIB, RS-232, RS-449 interface.

Code: [Select]
IA File: IHPIB_I
IA Description: "HPIB IA FOR INTERFACE        1_0"
IA Field Option: A

IA File: IRS232_I
IA Description: "RS232 IA FOR INTERFACE       1_0"
IA Field Option: A

IA File: IRS449_I
IA Description: "RS449 IA FOR INTERFACE       1_0"
IA Field Option: A
 
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Offline TimInCanada

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #30 on: June 05, 2018, 08:03:28 pm »
Wow!  I am in absolute awe of you guys.  Well Done!  :clap:

Mark: I still can't get my 16702B/16712A to load the formatted 6800 IA, but the IA Format utility is happy with the .R file you came up with.  Thank you.

Tim
 

Online sleary78

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #31 on: September 13, 2018, 03:50:56 pm »
I am using my HP1661CS with the ethernet option so i knocked up a python script to replace IALDOWN

https://pastebin.com/BfLZfBmj

Probably buggy but it works just like the original.
 

Offline jackrubin

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #32 on: December 18, 2018, 04:43:18 pm »
Wow! Just stumbled across this post on a topic that I haven't thought much about for the last few years. Great to see the current work and gslick still going at it! Thanks to Glenn, Mark and all the other contributors.

Best to all and a HP New Year!
Jack

*************
BTW, I'm not sure the license file - "The 16700 analyzers have the B4620B Software Correlation Tool option.  The analyzer comes with the tool installed, but needs a license to use.  Fortunately, the license file is available for non-commercial use (along with licenses for the other options)." - mentioned above made the transition from Yahoo groups to groups.io.

Can anyone point to a copy of it? I'll be happy to add it to Groups.io Agilent group

Thanks -

« Last Edit: December 18, 2018, 04:53:17 pm by jackrubin »
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #33 on: December 18, 2018, 09:30:55 pm »
BTW, I'm not sure the license file - "The 16700 analyzers have the B4620B Software Correlation Tool option.  The analyzer comes with the tool installed, but needs a license to use.  Fortunately, the license file is available for non-commercial use (along with licenses for the other options)." - mentioned above made the transition from Yahoo groups to groups.io.

Can anyone point to a copy of it? I'll be happy to add it to Groups.io Agilent group
The license file is text.  The content of the file is embedded in a post, so it got moved from yahoo and it's still there.

In the HP-Agilent-Keysight group, search for "16700 software tool sets" for a post from Apr 17 24, 2015.  Then search for "HP/Agilent 16702 Software Tools License Keys" for a followup spelling correction to the InfiniBand key.

EDIT: Correction on the date - it was Apr 24, not the 17th.
« Last Edit: December 22, 2018, 04:32:02 pm by MarkL »
 
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Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #34 on: January 04, 2019, 12:57:21 am »
I did some experimenting with the network protocol inverse assembler (aka. protocol decoder) on a 16702B logic analyzer and mikeselectricstuff's new etherdecode board.  I'm dropping a link in this thread since some of you IA fans may want to know how to set up and use the INETWRKE inverse assembler:

  https://www.eevblog.com/forum/testgear/ethernet-trigger-an-protocol-decoding-for-mso-or-logic-analyser/msg2088775/#msg2088775

It doesn't have to be used with Mike's board, but I thought it would be a fun way to learn more about the 16700 series capabilities and make Mike's board easier to use.

If you have questions specifically about the analyzer setup, it might be better to post them here so we don't throw Mike's thread too far off-topic.
 

Offline nemike

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #35 on: February 16, 2019, 10:42:14 pm »
I'm trying to load an inverse assembler for 68010 from invasm_v3 on my 1670d (latest firmware), I only recently got it and am trying to learn to use it but haven't had much success in understanding how to load an inverse assembler.  I downloaded invadm_v3 and while I can select "load analyzer from i68010_p" (shows file type: inverse_assem) it says "No state machines for this module", if I configure it as follows:

Label  0: ADDR     (24 bits):  A3: ******** ........  A2: ******** ********
Label  1: DATA     (16 bits):  A1: ******** ********
Label  2: STAT     ( 8 bits):  A3: ........ ********
Label  3: SIZE     ( 2 bits):  A3: ........ .....**.
Label  4: VMA      ( 1 bits):  A3: ........ ....*...
Label  5: FC       ( 3 bits):  A3: ........ .***....

And then "load analyzer from i68010_p" it flashes the asterisk in the top right but nothing seems to happen and when I go to config or waveform or listing I don't see anything...  What am I missing?

Thanks, Mike
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #36 on: February 17, 2019, 07:13:28 pm »
...
And then "load analyzer from i68010_p" it flashes the asterisk in the top right but nothing seems to happen and when I go to config or waveform or listing I don't see anything...  What am I missing?

Thanks, Mike
I don't have a 1670 series to directly help with the issue you're seeing, but you might try loading the configuration file c68010_p instead.  In my reading of the manual, I think loading the configuration file should automatically load the associated inverse assembler after it has processed the configuration.  Maybe there's some other setup it needs to perform first.

The configuration files in that zip file are for a 16510 analyzer, but the manual says the 1670G should be able to read them.

Perhaps someone with a 1670 (or 16510) could help out more.
 

Offline nemike

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #37 on: February 18, 2019, 06:57:31 am »
I don't have a 1670 series to directly help with the issue you're seeing, but you might try loading the configuration file c68010_p instead.  In my reading of the manual, I think loading the configuration file should automatically load the associated inverse assembler after it has processed the configuration.  Maybe there's some other setup it needs to perform first.

The configuration files in that zip file are for a 16510 analyzer, but the manual says the 1670G should be able to read them.

Perhaps someone with a 1670 (or 16510) could help out more.

Thanks this helped, I was able to load the c68010_p and indeed the inverse assembler showed up in the listing section, but I did get some messages when it loaded:



This gave me the following format views:




I had setup my own configuration and format that looked like the c68010_p.txt file:



That is when I had tried to load the i68010_p file without error but it didn't seem to appear available in the listing view.

So I can use that 68010 as is but I can't use the invasm in my own configuration which might include other signals from elsewhere...

Thanks, Mike
« Last Edit: February 18, 2019, 07:01:41 am by nemike »
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #38 on: February 18, 2019, 07:13:04 pm »
I loaded c68010_p from invasm_v3 on a 16510 module in a 16500C and captured these resulting configuration screens.

Configuration:



Format:



Symbols:















Listing:






« Last Edit: February 18, 2019, 07:25:15 pm by gslick »
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #39 on: February 18, 2019, 07:41:54 pm »
If you connect your 1670D to a network so that you can do FTP transfers to the analyzer from another machine on the network, you can send the program file below to the 1670D to recreate the c68010_p configuration on the 1670D.

On the 1670D System - External I/O screen make sure the Controller is Connected To: Ethernet (instead of HPIB or RS-232C). Then on the 1670D System - External I/O screen make sure the LAN Settings - Analyzer IP Address is appropriate for your network.

Then you can open an FTP connection to the 1670D from another system on your network and login as user "control". Then "cd /system", then "put program", assuming that the program below is saved to a file named "program" on system on which you are running FTP.

This program assumes that the invasm file "I68010_P" has been copied to the directory "\INVASMV3" on the hard drive of the 1670D.

I verified that this works on my 1670D.

Code: [Select]
:SELECT 1
:MACHINE1:NAME '68010'
:MACHINE1:ASSIGN 1,2,3,4
:MACHINE1:TYPE STATE
:MACHINE2:TYPE OFF
:MACHINE1:SFORMAT:MASTER J, RISING
:MACHINE1:SFORMAT:REMOVE ALL
:MACHINE1:SFORMAT:LABEL 'ADDR', POSITIVE, #H0, #H0000, #HFF00, #HFFFF, #H0000
:MACHINE1:SFORMAT:LABEL 'DATA', POSITIVE, #H0, #H0000, #H0000, #H0000, #HFFFF
:MACHINE1:SFORMAT:LABEL 'STAT', POSITIVE, #H0, #H0000, #H00FF, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'SIZE', POSITIVE, #H0, #H0000, #H0006, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'VMA',  POSITIVE, #H0, #H0000, #H0008, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'FC',   POSITIVE, #H0, #H0000, #H0070, #H0000, #H0000
:MMEMORY:CD '\INVASMV3', INTERNAL0
:MMEMORY:LOAD:IASSEMBLER 'I68010_P', INTERNAL0, 1, 1
:MMEMORY:CD '\', INTERNAL0
:MACHINE1:SYMBOL:REMOVE
:MACHINE1:SYMBOL:WIDTH 'STAT', 15
:MACHINE1:SYMBOL:BASE  'STAT', BINARY
:MACHINE1:SYMBOL:PATTERN 'STAT', 'DMA',             '#B0XXXXXXX'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER DATA WRITE', '#B1001XXX0'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER DATA READ',  '#B1001XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER PGRM READ',  '#B1010XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR DATA WRITE', '#B1101XXX0'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR DATA READ',  '#B1101XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR PGRM READ',  '#B1110XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'INTERRUPT ACK',   '#B1111XXXX'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'OPCODE FETCH',    '#B1X10XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'READ',            '#BXXXXXXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'WRITE',           '#BXXXXXXX0'
:MACHINE1:SYMBOL:WIDTH 'SIZE', 9
:MACHINE1:SYMBOL:BASE  'SIZE', BINARY
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'LOW BYTE',  '#B10'
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'HIGH BYTE', '#B01'
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'WORD',      '#B00'
:MACHINE1:SYMBOL:WIDTH 'VMA', 10
:MACHINE1:SYMBOL:BASE  'VMA', BINARY
:MACHINE1:SYMBOL:PATTERN 'VMA', '6800 CYCLE', '#B1'
:MACHINE1:SYMBOL:PATTERN 'VMA', '',           '#B0'
:MACHINE1:SYMBOL:WIDTH 'FC', 9
:MACHINE1:SYMBOL:BASE  'FC', BINARY
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER DATA', '#B001'
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER PROG', '#B010'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR DATA', '#B101'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR PROG', '#B110'
:MACHINE1:SYMBOL:PATTERN 'FC', 'INTR ACK',  '#B111'
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER',      '#B0XX'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR',      '#B1XX'
:MACHINE1:SYMBOL:PATTERN 'FC', '     DATA', '#BX01'
:MACHINE1:SYMBOL:PATTERN 'FC', '     PROG', '#BX10'
:MACHINE1:STRIGGER:CLEAR ALL
:MACHINE1:SLIST:REMOVE
:MACHINE1:SLIST:COLUMN 1, 'ADDR', HEXADECIMAL
:MACHINE1:SLIST:COLUMN 2, 'DATA', IASSEMBLER
:MACHINE1:SLIST:COLUMN 3, 'STAT', SYMBOL
:MACHINE1:SLIST:COLUMN 4, 'SIZE', SYMBOL
:MACHINE1:SLIST:COLUMN 5, 'VMA',  SYMBOL
:MACHINE1:SLIST:COLUMN 6, 'FC',   SYMBOL
:MACHINE1:SWAVEFORM:REMOVE
:MACHINE1:SWAVEFORM:INSERT 'ADDR', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'DATA', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'STAT', OVERLAY
:MENU 1,7
 

Offline Tom Swift

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #40 on: May 04, 2019, 07:37:22 am »
I don't get it.  I've tried them all and they all say the same thing.  What am I doing wrong?

Nevermind, gotta change it to 'Load' 'Analyzer' from file '<file>'

The c6809e_p.txt file says:

Title: 6809E CONFIG FOR GP PROBES   1_0

Pod assigments (? = disabled)
-----------------------------
Label  0: ADDR     (16 bits):  A2: ******** ******** 
Label  1: DATA     ( 8 bits):  A1: ........ ******** 
Label  2: STAT     ( 3 bits):  A1: .....*** ........ 

Symbols
-------
Label: STAT 
       INTR/RESET VECTR  01X
       SYNC ACKNOWLEDGE  10X
       HALT/BUS GRANT    11X
       WRITE             000
       READ              001


This is directly from the Motorola 6809 datasheet Page 6.

I'm guessing...
Pod A1: Channel 8 is to pin 32 of 6809E  (R//W)
Pod A1: Channel 9 is to pin 37 of 6809E (/RESET)
Pod A1: Channel 10 is to pin 40 of 6809E (/HALT)
Pod A1: Clk is to pin 34 of 6809E (E)

Is this correct?


Pod A1: Channel 8 is to pin 32 of 6809E  (R//W)
Pod A1: Channel 9 is to pin 5 of 6809E (BS)
Pod A1: Channel 10 is to pin 6 of 6809E (BA)
Pod A1: Clk is to pin 34 of 6809E (E)  (Still unsure about this one...)  (EDIT: This is correct)

Is this correct? (EDIT: This is correct)

So after all this I get:



Why isn't the address advancing?  It goes all the way to 4095 in the list.  RESET isn't LOW.
« Last Edit: May 05, 2019, 09:11:01 pm by Tom Swift »
 

Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #41 on: May 04, 2019, 11:42:22 pm »

Title: 6809E CONFIG FOR GP PROBES   1_0

Pod assigments (? = disabled)
-----------------------------
Label  0: ADDR     (16 bits):  A2: ******** ******** 
Label  1: DATA     ( 8 bits):  A1: ........ ******** 
Label  2: STAT     ( 3 bits):  A1: .....*** ........ 

Symbols
-------
Label: STAT 
       INTR/RESET VECTR  01X
       SYNC ACKNOWLEDGE  10X
       HALT/BUS GRANT    11X
       WRITE             000
       READ              001


Pod A1: Channel 8 is to pin 32 of 6809E  (R//W)
Pod A1: Channel 9 is to pin 5 of 6809E (BS)
Pod A1: Channel 10 is to pin 6 of 6809E (BA)
Pod A1: Clk is to pin 34 of 6809E (E)  (Still unsure about this one...)

Is this correct?

Why isn't the address advancing?  It goes all the way to 4095 in the list.  RESET isn't LOW.

I think you would want to clock on the falling edge of E. From the timing diagram it appears that both the address bus and the data bus should have stable and valid values at that point.

It does appear that using BA, BS, and R/W for the STAT signals would match the meaning of the MPU state definition according to those signals.

What happens if you trigger on address FFFF? There might be a lot of FFFE cycles when the reset condition first occurs.



 

Offline Tom Swift

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #42 on: May 05, 2019, 08:53:50 pm »
LOL!  I checked the wrong thread and wanted to reply.  Good call triggering on $FFFF.  So after going through all this, I have realized the data coming back after the initial vector read from $FFFE & $FFFF is getting corrupted.  I'll keep digging.  Thanks everyone!
 

Offline mmcgraw74

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #43 on: July 08, 2019, 12:14:23 am »
I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.

For example it contains this instruction opcode table. The opcode bit field positions vary in the instruction word based on the values of high order bits in the instruction word.

Code: [Select]
  /* definitions for the different unique bit patterns for each instruction
   * in the different instruction groups -- used by the interpreter
   */


I had a similar problem loading the C6800/02.I file on my HP 16500.

I solved it by manually creating the 6800 mapping from gslick's screenshots in this thread, including the User Symbols, making sure the machine name was 6800/02, then saving to the C6800/02 IA file.  Another file was created with that same name but newer timestamp - it was bigger, and also created a new config.txt file with that name.  Then I could power cycle my HP16500B and load the C6800/02.I file successfully.  I only had to change the User Symbol table back to Binary to see the symbols I had entered.
  /* instruction group 1 */
  const u_int16 IF_OP = 4;
  const u_int16 IF_BITS = 5;
  const u_int16 ICASE_OP = 6;
  const u_int16 ICASE_BITS = 7;

  /* instruction group 2 */
  const u_int16 IGO_TO = 4;
  const u_int16 ICALL = 5;
  const u_int16 ISTR_OUTPUT = 6;
  const u_int16 INUM_OUTPUT = 7;

  /* instruction group 3 */
  const u_int16 ILOAD_ACC = 8;
  const u_int16 IADD_ACC = 9;
  const u_int16 ISUB_ACC = 10;
  const u_int16 IAND_ACC = 11;
  const u_int16 IOR_ACC = 12;
  const u_int16 IXOR_ACC = 13;
  const u_int16 ITAG_WITH = 14;
  const u_int16 INP_ABS = 15;

  /* instruction group 4 */
  const u_int16 ISTORE_MEM = 4;
  const u_int16 INC_MEM = 5;
  const u_int16 IDEC_MEM = 6;
  const u_int16 INP_ABSQ = 7;

  /* instruction group 5 */
  const u_int16 INP_REL = 2;
  const u_int16 INP_RELQ = 3;

  /* instruction group 6 */
  const u_int16 IROT_LEFT = 8;
  const u_int16 IROT_RIGHT = 9;
  const u_int16 IEXT_BIT = 10;
  const u_int16 IPOS_ABS = 11;
  const u_int16 IPOS_REL = 12;

  /* instruction group 7 */
  const u_int16 INOP = 16;
  const u_int16 ICOMP_ACC = 17;
  const u_int16 ITWOCOMP_ACC = 18;
  const u_int16 IRETURN = 19;
  const u_int16 ION_TRACE = 20;
  const u_int16 IOFF_TRACE = 21;
  const u_int16 IABORT = 22;
  const u_int16 IFNOT_MAP = 23;
  const u_int16 IMARKLINE_O_NA = 24;
  const u_int16 IMARKLINE_S_NA = 25;
  const u_int16 IMARKLINE_O_A = 26;
  const u_int16 IMARKLINE_S_A = 27;
  const u_int16 IMARKSTATE_DISP = 28;
  const u_int16 IMARKSTATE_SUP = 29;
  const u_int16 INEWLINE = 30;
  const u_int16 IFETCH_POSITION = 31;

If I have this correct, the mapping from opcode words to instructions in .R files is the following:

Code: [Select]
/* instruction group 1 */
/* conditional instruction -- bit 15 is set */
/* instruction = (opcode >> 13) */

100x xxxx xxxx xxxx     IF_OP = 4
101x xxxx xxxx xxxx     IF_BITS = 5
110x xxxx xxxx xxxx     ICASE_OP = 6
111x xxxx xxxx xxxx     ICASE_BITS = 7

/* instruction group 2 */
/* transfer/output instruction -- bit 14 is set */
/* instruction = (opcode >> 12) */

0100 xxxx xxxx xxxx     IGO_TO = 4
0101 xxxx xxxx xxxx     ICALL = 5
0110 xxxx xxxx xxxx     ISTR_OUTPUT = 6
0111 xxxx xxxx xxxx     INUM_OUTPUT = 7

/* set immediate instruction -- bit 13 is on */

001x xxxx xxxx xxxx

/* instruction group 3 */
/* math instruction -- bit 12 is on */
/* instruction = (opcode >> 9) */

0001 000x xxxx xxxx     ILOAD_ACC = 8
0001 001x xxxx xxxx     IADD_ACC = 9
0001 010x xxxx xxxx     ISUB_ACC = 10
0001 011x xxxx xxxx     IAND_ACC = 11
0001 100x xxxx xxxx     IOR_ACC = 12
0001 101x xxxx xxxx     IXOR_ACC = 13
0001 110x xxxx xxxx     ITAG_WITH = 14
0001 111x xxxx xxxx     INP_ABS = 15

/* instruction group 4 */
/* single variable instruction -- bit 11 is on */
/* instruction = (opcode >> 9) */

0000 100x xxxx xxxx     ISTORE_MEM = 4
0000 101x xxxx xxxx     INC_MEM = 5
0000 110x xxxx xxxx     IDEC_MEM = 6
0000 111x xxxx xxxx     INP_ABSQ = 7

/* instruction group 5 */
/* input relative instruction -- bit 10 is on */
/* instruction = (opcode >> 9) */

0000 010x xxxx xxxx     INP_REL = 2
0000 011x xxxx xxxx     INP_RELQ = 3

/* instruction group 6 */
/* single operand instruction -- bit 9 is on */
/* instruction = (opcode >> 6) */

0000 0010 00xx xxxx     IROT_LEFT = 8
0000 0010 01xx xxxx     IROT_RIGHT = 9
0000 0010 10xx xxxx     IEXT_BIT = 10
0000 0010 11xx xxxx     IPOS_ABS = 11
0000 0011 00xx xxxx     IPOS_REL = 12

/* instruction group 7 */
/* implied operand instruction - bits 15-5 off, bit 4 on */

0000 0000 0001 0000     INOP = 16
0000 0000 0001 0001     ICOMP_ACC = 17
0000 0000 0001 0010     ITWOCOMP_ACC = 18
0000 0000 0001 0011     IRETURN = 19
0000 0000 0001 0100     ION_TRACE = 20
0000 0000 0001 0101     IOFF_TRACE = 21
0000 0000 0001 0110     IABORT = 22
0000 0000 0001 0111     IFNOT_MAP = 23
0000 0000 0001 1000     IMARKLINE_O_NA = 24
0000 0000 0001 1001     IMARKLINE_S_NA = 25
0000 0000 0001 1010     IMARKLINE_O_A = 26
0000 0000 0001 1011     IMARKLINE_S_A = 27
0000 0000 0001 1100     IMARKSTATE_DISP = 28
0000 0000 0001 1101     IMARKSTATE_SUP = 29
0000 0000 0001 1110     INEWLINE = 30
0000 0000 0001 1111     IFETCH_POSITION = 31
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #44 on: May 06, 2020, 11:34:41 pm »
Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.

I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.

A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.

I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.

Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.
 
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Online TK

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #45 on: May 07, 2020, 12:06:49 am »
Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.

I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.

A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.

I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.

Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.
The adapters look nice but I think they are not designed to match the wiring the inverse assembler expects.  i.e. the original HP 6502 Z80 adapter requires some logic circuitry to simulate delays and also the inverse assembler configuration file expects specific signals in certain pins.  The analyzer operates in state mode and needs to use the clock inputs in the PODs.

EDIT: Z80, not 6502
« Last Edit: May 07, 2020, 12:14:39 pm by TK »
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #46 on: May 07, 2020, 12:21:06 am »
Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.

I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.

A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.

I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.

Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.
Installation guide: https://www.keysight.com/upload/cmc_upload/All/16700710.pdf

It appears to be the HP-UX based analyzer.  You should be able to connect a monitor, keyboard and mouse and connect through X-Windows
 
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Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #47 on: May 07, 2020, 04:46:28 am »
Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?

Oh - in regard to the 6502 adapter - is there a schematic available? Or does anyone have one that can be reverse engineered? I'm happy to throw a board together once I know what logic is required. I'll check the config files that have been generated for the pin info.

Trying to find an original 6502 adapter would be pretty tough going I expect.

EDIT : It appears that there is no 6502 inverse assembler within the uploaded files - is it still available somewhere?
« Last Edit: May 07, 2020, 05:39:21 am by deanclaxton »
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #48 on: May 07, 2020, 12:22:02 pm »
Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?

Oh - in regard to the 6502 adapter - is there a schematic available? Or does anyone have one that can be reverse engineered? I'm happy to throw a board together once I know what logic is required. I'll check the config files that have been generated for the pin info.

Trying to find an original 6502 adapter would be pretty tough going I expect.

EDIT : It appears that there is no 6502 inverse assembler within the uploaded files - is it still available somewhere?
Sorry, the adapter information was for the Z80: https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485

The 6502 inverse assembler was written by someone else and it was made available through download.  Source files:https://stardot.org.uk/forums/viewtopic.php?t=11043
 
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Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #49 on: May 07, 2020, 01:39:03 pm »
Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?
...
It sounds like you might have the "missing pullup resistor" problem, the same as the 167xx series:

  https://www.eevblog.com/forum/testgear/hp-16702a-mouse/msg374967/#msg374967

Sometimes non-Agilent keyboards and mice work, sometimes they don't.
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #50 on: May 07, 2020, 09:41:32 pm »
Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?
...
It sounds like you might have the "missing pullup resistor" problem, the same as the 167xx series:

  https://www.eevblog.com/forum/testgear/hp-16702a-mouse/msg374967/#msg374967

Sometimes non-Agilent keyboards and mice work, sometimes they don't.
Interesting - I have a bunch of cheap PS2 mice I purchased a while ago (like 10 for $10 or something silly) that were to be used on the analyser (well, one of them anyway!) but didnt work - hopefully this might fix it :) Will fire up the old girl at the weekend and try get it up and running - I'm very keen to get the 6502 setup working - I'll aim to make an adapter PCB to make it fast to set it up, else its too much of a hassle to connect all the probes. The adapter I linked to earlier seems to have the termination network (2 resistors and a capacitor) per signal but no logic - I guess something along the lines of the Z80 one would be a starting point but it would be nice to find someone who has one and replicate it.

Are the 40 pin pod connector pinouts fairly standard across the HP 16xx(x) range? Initial board will be for the HP 16xxx as that is what I have on hand.
« Last Edit: May 07, 2020, 09:44:13 pm by deanclaxton »
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #51 on: May 07, 2020, 10:41:41 pm »
The 40-pin pod connector is fairly standard.  If you want to play with inverse assemblers, make sure to create the adapter following the configuration file pinout for the ADDR, DATA and STAT signals as defined in the inverse assembler configuration file.  Connecting the POD pins to a 6502 or Z80 is not that difficult, just 16 address lines, 8 data lines and around 4 stat lines including correct clock combinations.
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #52 on: May 08, 2020, 06:20:27 am »
The 40-pin pod connector is fairly standard.  If you want to play with inverse assemblers, make sure to create the adapter following the configuration file pinout for the ADDR, DATA and STAT signals as defined in the inverse assembler configuration file.  Connecting the POD pins to a 6502 or Z80 is not that difficult, just 16 address lines, 8 data lines and around 4 stat lines including correct clock combinations.

Will do. I have a 6502 IA here : https://www.dropbox.com/s/bjot0hxo9695s35/ia6502.zip?dl=0

Its not clear from the .S file which pod pins go where but it does list the input status bits and clocking on the falling edge of phi 2 :

************************************************************************
* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.
*

I'll have to read back through this thread to understand how to pull the required info from the other files.
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #53 on: May 08, 2020, 04:09:02 pm »
In 6502.S, the CASE_OF statement on line 101 says that it only cares about bits 4 through 1 of the STAT column.

So, the STAT column needs 5 signals assigned to it (MSB to LSB): R/W, RST, NMI, INT, and <anything>.  You can assign SYNC to bit 0 if you want.

The bit numbers shown in the beginning of 6502.S are probably just the assignments for those signals coming in from a probe pod.  You don't have to use those exact assignments, as long as the bits in your STAT column are defined in the order above.

That should work, but caveat that I don't have a 6502 to verify it.
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #54 on: May 08, 2020, 08:29:24 pm »
Ah ok. Do these files lock in particular pods and pod signals that it expects to be connected to data and address busses?

Ie pod 3, signal 0 = address 0?

I suppose this will all become clear once I get my unit up and running :)
« Last Edit: May 08, 2020, 08:44:36 pm by deanclaxton »
 

Offline MarkL

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #55 on: May 08, 2020, 10:13:52 pm »
The signal mapping is completely flexible.

Connect up the pods as you like.  But to keep things sane, you should probably assign one pod to the ADDR lines, and one pod to STAT and DATA signals.  Preserve the ordering of MSB to LSB for the data and address lines.

The physical to logical mapping for each incoming probe signal is done in the pod assignment tab.  The field (column) names ADDR, DATA, and STAT are significant to the IA.  The IA expects to find the address signals from A15 to A0 assigned to ADDR, D7 to D0 to DATA, and the control signals to STAT as previously noted.

If you haven't used one of these LAs before, take a stroll through the help when you get your system running.  It's context sensitive, and it's the main source of documentation for all HW and SW operations.

The help files are also available on keysight.com in PDF under the various 167xx product home pages, but they're a bit scattered.  You have to look at each product home pages to really find everything.
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #56 on: May 08, 2020, 11:33:25 pm »
Thanks Mark - thats excellent. I've got it up and running - turns out the previous owner had done a complete rebuild before passing it on. I found a mouse (MS Intellimouse 1.1A USB with PS2 adapter) and keyboard (IBM KB-0225 PS2 keyboard) that work and am currently using the VGA output. I believe all the optional licenses are installed already as well. It has some IA's installed as well so I loaded up a 68000 one to take a look. I can see the pod assignment and under the fomat tab it shows all the various mapping (lots of signals mapped in).

Question for now would be whether the 6502 signals would need any timing adjustment as per the Z80 example where each signal is buffered plus a few are slightly delayed via additional gates etc. I'll throw together an initial adapter board and give it a go. If the logic analyser is set to sample the data on the falling edge of the phi2 clock (in the case of the 6502 example), would a delay ensure that the signals are valid when the analyser samples them - ie is it possible that it would otherwise sample the signals before they are valid - by delaying the phi2 clock signal a few ns perhaps ensures the bus data is valid when sampled? I guess I need to look at the 6502 datasheet for that info, and to actually start playing around with it to work it all out. In general I wonder if cpu adapters sold by vendors would buffer all the bus signals (as per the Z80 one), and why that might be required.

EDIT : Ah - reading back in the thread here (https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485) it seems that the Z80 timing is more complex - seems that TK was using the 6502 inverse assembler directly, so perhaps I wont need anything on my adapter other than the termination. Will give it a go!

« Last Edit: May 09, 2020, 12:19:33 am by deanclaxton »
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #57 on: May 09, 2020, 03:03:12 am »
It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA
 

Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #58 on: May 09, 2020, 03:23:03 am »
It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA

Thanks TK - is is possible to see your configuration as to which pod pins you used to interface to the 6502? Also did you use the IA from Phil Pemberton or another one?
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #59 on: May 10, 2020, 10:52:18 pm »
I said:
The signal mapping is completely flexible.

Connect up the pods as you like.  But to keep things sane, you should probably assign one pod to the ADDR lines, and one pod to STAT and DATA signals.  Preserve the ordering of MSB to LSB for the data and address lines.
...

It dawned on me today that you said you have a 16602A.  I don't have one to verify, but I don't believe arbitrary bit ordering is supported on it.  That feature seems to have been added in an early 2.xx release, and a recent post in the HPAK groups.io says that the 16600 series doesn't run version 2.xx.

So... What I said about ADDR, DATA, and STAT is still true, expect you DO have to connect the signals in the right physical order of MSB to LSB (consecutively) so that the logical bits are also in the same order when you define those labels.  A minor detail, but I didn't want to leave you with incorrect info, wondering what I was talking about.

On the setup and hold question, the spec sheet says that the 16602A has an adjustable setup and hold time of 0 to 4.5ns, if you run into trouble with delay.
 
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Offline gslick

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #60 on: May 11, 2020, 12:42:39 am »
It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA

Thanks TK - is is possible to see your configuration as to which pod pins you used to interface to the 6502? Also did you use the IA from Phil Pemberton or another one?

This is how I configured a 1670 series analyzer to use the 6502 inverse assembler:





 
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Offline philpem

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #61 on: May 12, 2020, 08:26:17 am »
Its not clear from the .S file which pod pins go where but it does list the input status bits and clocking on the falling edge of phi 2 :

************************************************************************
* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.
*

That's the inverse assembler I wrote back while I was in my late teens... I was building a 6502 SBC and wrote an IA to help debug it.

To get it working, you hook the CPU address bus up to one pod (16 bits) and declare it as ADDR in the IA. Hook the data bus up to the low half of the other probe and declare it as DATA. Hook up the STAT lines as above. The bits refer to the bit assignments in the STAT word -- from memory, I assigned the whole top byte to STAT then declared separate labels for the individual pins.

Connect PHI2-Out from the 6502 to the J-clock or K-clock. Set that as your storage clock, triggered on a H->L edge.

The IA's written for the Western Design Center W65C02S, so it supports the extended instructions (at least the ones supported by that particular chip).

There was never a test adapter. I shoved a DIN41612 connector into the backplane and wired up pods to the back of it. These days if I was planning to use the rig more than once, I'd use the 20way IDC, Samtec or Mictor transition adapters and spin a PCB...

Glad to see this crusty old code is still useful nearly 20 years later! Shame I forgot to stick my name on it, though I didn't expect it to spread far!
It came with a version of IALDOWN I wrote in Borland Delphi because the DOS one didn't work under Windows.

My notes on IAL are probably still floating around, I ripped apart the IAL .R format and instruction set during a break at university.

Cheers,
Phil.
Phil / M0OFX -- Electronics/Software Engineer
"Why do I have a room full of test gear? Why, it saves on the heating bill!"
 
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Offline deanclaxton

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #62 on: May 12, 2020, 10:29:33 am »
Wow - thats awesome - thanks Phil! I'm going to lay out a PCB for this - probably with a jumper to select which clock (phi0, 1, or 2) wires to the pod, and also include a couple of clip points for +5V and GND which would give me a handy location to safely connect a logic probe, scope ground lead, etc (for additional troubleshooting on a board).

There are a few leftover pod signal lines that could pick up the remaining signals on a 6502 (SO, RDY) for timing analysis/general troubleshooting, however the 65C02 has a few more again (MLB, BE, VPB). VPB (pin 1) is another GND on a 6502. Rather than use another pod connector, I might have to decide which of these signals are must - haves. Will check out some of the boards I'd be troubleshooting to determine which were used commonly.
« Last Edit: May 12, 2020, 10:49:02 am by deanclaxton »
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #63 on: June 02, 2020, 07:20:47 pm »
hi to all and thanks for this epic thread !
I'm new owner of HP 16500A, I have timing/state modules the one with ID 31
When I try to load any invasm ( would like to use it for z80 ) i got SOFTWARE ERROR - Please record these number  0010 0000006E 2000
My unit is with 1MB ram and Operating System v.6.
Thanks
 

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #64 on: June 02, 2020, 11:48:38 pm »
hi to all and thanks for this epic thread !
I'm new owner of HP 16500A, I have timing/state modules the one with ID 31
When I try to load any invasm ( would like to use it for z80 ) i got SOFTWARE ERROR - Please record these number  0010 0000006E 2000
My unit is with 1MB ram and Operating System v.6.
Thanks

I just tried loading some of the INVASM files on a 16510A analyzer module installed in a 16500A mainframe with a 1MB CPU running Version 6.00 of the system software and they seemed to load fine for me without any error.

Maybe something went wrong with the method you used to create the floppy disks you are using. Do you have a PC with a 3.5-inch floppy drive that you can use to boot into real mode MS-DOS? If you can download and run ImageDisk 1.18 on a PC in real mode MS-DOS I have attached an ImageDisk image of a 720-KB LIF format floppy disk (not a 1.44MB HD floppy disk) that contains the 16500A Version 6.00 SYSTEM_ and SYSTEM_031 files plus some Config and IA files that I was able to load without errors.

ImageDisk 1.18 download link here:
http://www.classiccmp.org/dunfield/img/index.htm

Code: [Select]
DISK DIRECTORY                                                                 

DOS Filename  Date    Time     Bytes   Description
____________  _______ ________ _______ ________________________________

C68000_P       2Jun20 13:05:19   18944 68000 CONFIG FOR GP PROBES   1_0
C68008_P       2Jun20 13:05:50   18944 68008 CONFIG FOR GP PROBES   1_0
C6800_P        2Jun20 13:06:11   18432 6800/02 CONFIG FOR GP PROBES 1_0
C68010_P       2Jun20 13:06:32   18944 68010 CONFIG FOR GP PROBES   1_0
C6809E_P       2Jun20 13:06:52   18432 6809E CONFIG FOR GP PROBES   1_0
C6809_P        2Jun20 13:07:08   18432 6809 CONFIG FOR GP PROBES    1_0
C8085_P        2Jun20 13:07:29   18432 8085 CONFIG FOR GP PROBES    1_0
I68000_P       2Jun20 13:07:50    9216 68000 IA FOR GP PROBES       1_0
I68008_P       2Jun20 13:08:05    9728 68008 IA FOR GP PROBES       1_0
I6800_P        2Jun20 13:08:21    9216 6800/02 IA FOR GP PROBES     1_0
I68010_P       2Jun20 13:08:37    9984 68010 IA FOR GP PROBES       1_0
I6809E_P       2Jun20 13:08:54   10240 6809E IA FOR GP PROBES       1_0
I6809_P        2Jun20 13:09:09   10240 6809 IA FOR GP PROBES        1_0
I8085_IP       2Jun20 13:09:39    5120 8085 INVERSE ASSEMBLER       1_0
SYSTEM_       31Oct89  0:02:00  233728 HP16500A System Software  V06.00
SYSTEM_031    31Oct89  0:02:00  252160 35MHz State/100MHz Timing V06.00

 
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Offline xadhoom76

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #65 on: June 03, 2020, 08:42:00 am »
Great it WORKS !!! Thanks Master !
 

Offline xadhoom76

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Re: HP Logic Analyzer Inverse Assemblers
« Reply #66 on: June 04, 2020, 06:16:15 am »
In my test I use lifutil but the files listed on HP16500A seems to miss some
Your listing
DISK DIRECTORY                                                                 

DOS Filename  Date    Time     Bytes   Description
____________  _______ ________ _______ ________________________________

C68000_P       2Jun20 13:05:19   18944 68000 CONFIG FOR GP PROBES   1_0
C68008_P       2Jun20 13:05:50   18944 68008 CONFIG FOR GP PROBES   1_0
C6800_P        2Jun20 13:06:11   18432 6800/02 CONFIG FOR GP PROBES 1_0
C68010_P       2Jun20 13:06:32   18944 68010 CONFIG FOR GP PROBES   1_0
C6809E_P       2Jun20 13:06:52   18432 6809E CONFIG FOR GP PROBES   1_0
C6809_P        2Jun20 13:07:08   18432 6809 CONFIG FOR GP PROBES    1_0
C8085_P        2Jun20 13:07:29   18432 8085 CONFIG FOR GP PROBES    1_0
I68000_P       2Jun20 13:07:50    9216 68000 IA FOR GP PROBES       1_0
I68008_P       2Jun20 13:08:05    9728 68008 IA FOR GP PROBES       1_0
I6800_P        2Jun20 13:08:21    9216 6800/02 IA FOR GP PROBES     1_0
I68010_P       2Jun20 13:08:37    9984 68010 IA FOR GP PROBES       1_0

If I add cz80_P and iz80_i it doesn't work and i notice the file is missing the description.

My add using lifutil could be wrong ?
I work in dos directly booting from a floppy on my old pc. then lifutil and I choos dos to lif .
I try different format of files ( DFS or other ) but no way to make it working.
Sorry to bored you but really do not understand why.
I would like to use 16500A with z80 and 6502
Best regards and thanks. I will try again , your floppy works great.
 


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