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| Just got a Tek 2465A, couple questions (how I screwed the calibration data)!! |
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| alpher:
I've tried the 2465a_test_3.bin in both sockets U2160 and U2260 four times, once with jumper P503 in normal position and once in CAL, 4 times no-go. Pin 12 of U2310 goes up to ~ 1V, looks like something is pulling it down? Anyway I've tried it a few times pulling ROMs, putting them back between the trials, running excersiser 02 of course. No matter what I did it did not write SRAM!! >:( Decided in favour of "atomic" option, dumped the SRAM and installed the NVRAM, ST equivalent of Dallas 1225 chip, here are some pics: Of course I programmed the NVRAM with an image with modified calib. constants, used usuthu65 values. The result of the scope boot up is here: So no more test 04 fail, looks like that was taken care of the calibration constants from usuthu65's scope. Guess I have to readup on the options for the 2465A, mine is a CT version and that obviously is a problem. Good news for people that backed up their calibration constants via excersiser 02 or othervise is that once properly written back to the memory you'll probably going to be god to go. For me not so much as I have yet to see an CT version of the calib. constants posted. Really appreciate if anyone with a 2465A CT is willing to run the exreciser 02 and post the footage, that would be great. Anyway some progres finally. :) |
| MarkL:
--- Quote from: alpher on April 03, 2018, 12:41:20 am ---I've tried the 2465a_test_3.bin in both sockets U2160 and U2260 four times, once with jumper P503 in normal position and once in CAL, 4 times no-go. Pin 12 of U2310 goes up to ~ 1V, looks like something is pulling it down? Anyway I've tried it a few times pulling ROMs, putting them back between the trials, running excersiser 02 of course. No matter what I did it did not write SRAM!! >:( Decided if favour of "atomic" option, dumped the SRAM and installed the NVRAM, ST equivalent of Dallas 1225 chip, here are some pics: --- End quote --- Oh well, I really thought I had it that time around. I wish I had a way to test it. Thanks for giving it a try. I did find the programming info for the PAL, and U2160 is the boot socket, FWIW. The remainder of the description in the service is consistent with the PAL programming. I wonder if it's stuck in a loop and U2310 pin 12 actually has a pulse on it. Maybe I'll figure it out when my 2465A controller board gets here. I'm still interested in knowing what was wrong. I'll post any results here for future 2465A users. But I'm glad you were successful with the posted calibration constants (except for the CT, that is). The CT is pretty easy to calibrate. All you need is an accurate 1MHz 1Vp-p square wave. I'm not sure about error code 81 03, however. It's not listed in the manual I have. Maybe my version from Jun 87 is outdated. |
| alpher:
--- Quote from: MarkL on April 03, 2018, 01:32:22 am --- --- Quote from: alpher on April 03, 2018, 12:41:20 am ---I've tried the 2465a_test_3.bin in both sockets U2160 and U2260 four times, once with jumper P503 in normal position and once in CAL, 4 times no-go. Pin 12 of U2310 goes up to ~ 1V, looks like something is pulling it down? Anyway I've tried it a few times pulling ROMs, putting them back between the trials, running excersiser 02 of course. No matter what I did it did not write SRAM!! >:( Decided if favour of "atomic" option, dumped the SRAM and installed the NVRAM, ST equivalent of Dallas 1225 chip, here are some pics: --- End quote --- Oh well, I really thought I had it that time around. I wish I had a way to test it. Thanks for giving it a try. I did find the programming info for the PAL, and U2160 is the boot socket, FWIW. The remainder of the description in the service is consistent with the PAL programming. I wonder if it's stuck in a loop and U2310 pin 12 actually has a pulse on it. --- End quote --- Don't think so, I have a Rigol 1054Z and it was setup to single shoot at 2v on pin 12 of U2310, never did. I'm on the opinion that there is some sort of write protection of the calib. data under normal operation. It may involve the PAL, who knows. To me it makes sense, if I was the one developing the software for such a machine, I certainly would've want some sort of hardware protection against accidental writes to the calibration data memory area. |
| MarkL:
--- Quote from: alpher on April 03, 2018, 01:54:40 am ---Don't think so, I have a Rigol 1054Z and it was setup to single shoot at 2v on pin 12 of U2310, never did. I'm on the opinion that there is some sort of write protection of the calib. data under normal operation. It may involve the PAL, who knows. To me it makes sense, if I was the one developing the software for such a machine, I certainly would've want some sort of hardware protection against accidental writes to the calibration data memory area. --- End quote --- Ok, so much for the pulse theory on U2310 pin 12. The CAL jumper is only a switch input to the processor, like a front panel button. You can see it on schematic <2> location 7E. It doesn't provide any hardware protection. Here's some more detail on how the SRAM operates. On the SRAM, CE2 is enabled whenever nRESET is high. Other SRAM inputs are controlled by the PAL: nOE = ~( nWFF ) nWE = ~( E & ~RD ) nCE1 = ~OR( E & VMA & PAGE & A15 & ~A14 & ~A13, E & VMA & ROM & A15 & ~A14 & ~A13, E & VMA & & ~A15 & ~A14 & ~A13 & ~A12 & ~A11 ) nWFF = U2440B.9 = delayed write, described in service manual theory under "Timing Logic". And since I'm looking at the PAL... The two EPROMS have their A15 input tied to PAGE. So the PAGE signal selects either the lower or upper half of each EPROM address space. The EPROMS are then enabled by outputs from the PAL (A15 below is the A15 output from the processor): U2160 nOE = ~OR( E & RD & VMA & ~ROM & ~PAGE & A15, E & RD & VMA & ~ROM & PAGE & A15 & A14, E & RD & VMA & ~ROM & PAGE & A15 & A13 ) U2260 nOE = ~OR( E & RD & VMA & ROM & ~PAGE & A15 & A14, E & RD & VMA & ROM & ~PAGE & A15 & A13, E & RD & VMA & ROM & PAGE & A15 & A14, E & RD & VMA & ROM & PAGE & A15 & A13 ) Here's what all this means. The two 64k EPROMs are arranged in 4 banks of 32768 bytes. ROM=0 selects U2160, and ROM=1 selects U2260. PAGE=0 selects the lower half, PAGE=1 selects the upper half. At reset PAGE and ROM are both 0. A15 from the processor must always be 1 to enable the EPROMs. So, to execute code out of the EPROMs the program counter must stay 8000 - ffff. If either PAGE=1 or ROM=1, it creates a hole in the address space for the entire SRAM to drop in at 100x.xxxx.xxxx.xxx (8000 - 9fff). The lower portion of SRAM is always accessible at 0000.0xxx.xxxx.xxxx (0000 - 07ff). ROM and PAGE are controlled by writing to port 0x08c0. ROM is bit 0x08 and PAGE is bit 0x10. Bank switching is immediate in this system, so if you're executing from the EPROM and you change ROM or PAGE, you will suddenly be executing from a different section and/or different EPROM. The addresses where the switching is occurring need to be coordinated. It could also be done by writing a little bank switch routine into the SRAM and jumping to that. I don't know which Tek is doing. Attached is the JEDEC file for the PAL and my notes derived from that, if anyone is interested or wants to tell me what I got wrong in any of the above or the SRAM writer code (posted a few messages ago). PAL datasheet here: http://datasheet.octopart.com/TIBPAL16L8-25CN-Texas-Instruments-datasheet-10254311.pdf |
| MarkL:
--- Quote from: alpher on April 03, 2018, 12:41:20 am ---... Pin 12 of U2310 goes up to ~ 1V, looks like something is pulling it down? ... --- End quote --- Just on this one point, that's odd because U2310 is an LS174 6-bit latch and pin 12 is one of the totem-pole outputs. If it's not pulsing, it should be nailed to a low or high and not something in between (like 1V). The only thing I can think of at the moment is if you had the unit in diag mode when you made the measurement. The diag jumper removes power from U2310 (and U2350 and U2450). If that's the case I could imagine pin 12 might have settled at some strange level. |
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