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Low cost logic analyzer probe for Rigol MSO5000 EasyEDA project
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S. Petrukhin:
Chinese comrades are having a blast...   |O
However, I lived in the USSR and understand a little how the system works...  8)
nctnico:
I strongly recommend to design for the regular cable and not use tricks like mirroring.  It will get messy at some point. You can mount the connectors on different sides of the flat cable without changing the order of the pins to achieve the same.
S. Petrukhin:

--- Quote from: nctnico on June 07, 2020, 12:41:03 am ---I strongly recommend to design for the regular cable and not use tricks like mirroring.  It will get messy at some point. You can mount the connectors on different sides of the flat cable without changing the order of the pins to achieve the same.

--- End quote ---

OK, I'll change the angle connector to the regular and make the design for the regular cable.
Using a angle connector with a regular cable is very inconvenient.

Give me a few hours for a new design.
S. Petrukhin:
OK, friends!

The new design is complete.
It is in the same project as version 2.0.

Thank you all for your help and participation.
nctnico:
I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver.
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