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| Low cost logic analyzer probe for Rigol MSO5000 EasyEDA project |
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| S. Petrukhin:
--- Quote from: nctnico on June 08, 2020, 12:30:02 am ---I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver. --- End quote --- I'm not sure exactly about LVDS, but the terminating resistor is placed on both sides of a symmetrical line, isn't it? Correct me if I'm wrong. In any case, you can not install these resistors at will. |
| ebclr:
Your English is just fine, Don't worry about |
| Gandalf_Sr:
--- Quote from: nctnico on June 08, 2020, 12:30:02 am ---I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver. --- End quote --- I asked about this here. The answer was that the guts of the MSO5000 don't appear to have any terminating resistors - I think the internal IC inputs are RSPECL. So you have to terminate the LVDS signals (which are current signals) on a 100 or 120 Ohm resistor to convert them to voltages. Keep reading from my link and you'll see a load of discussion on that page. In some respects I was designing a circuit with an output into an unknown input although there are some good breakdown photos. Anyway, I have these LVDS terminating resistors on my design and it works with them and it doesn't work without them. Long story short, I think Sergey is right to include the terminating resistors. |
| S. Petrukhin:
--- Quote from: Gandalf_Sr on June 08, 2020, 02:40:50 pm --- --- Quote from: nctnico on June 08, 2020, 12:30:02 am ---I took a look at your schematics. Why are there 100 Ohm resistors between the LVDS signals at the driver side? These shouldn't be there. LVDS is terminated at the receiver. LVDS is a current sourcing/sinking signaling system and adding extra load is reducing the swing at the receiver. --- End quote --- I asked about this here. The answer was that the guts of the MSO5000 don't appear to have any terminating resistors - I think the internal IC inputs are RSPECL. So you have to terminate the LVDS signals (which are current signals) on a 100 or 120 Ohm resistor to convert them to voltages. Keep reading from my link and you'll see a load of discussion on that page. In some respects I was designing a circuit with an output into an unknown input although there are some good breakdown photos. Anyway, I have these LVDS terminating resistors on my design and it works with them and it doesn't work without them. Long story short, I think Sergey is right to include the terminating resistors. --- End quote --- Yes, I also looked at the photo - there the connector pins are connected to an array of resistors on the visible layer. There may be tracks on the inner layer for terminating resistors, but you can't see the tracks and resistors. And I looked at how it is done on your disign. :) But why do you say it's a current line? Maybe I not understand the terminology in English, but this is not a line like 4..20 mA, where the signal is transmitted by current. Aren't these resistors the matching ones for the wave resistance? |
| Gandalf_Sr:
--- Quote from: S. Petrukhin on June 08, 2020, 03:12:27 pm ---...But why do you say it's a current line? Maybe I not understand the terminology in English, but this is not a line like 4..20 mA, where the signal is transmitted by current. Aren't these resistors the matching ones for the wave resistance? --- End quote --- If you look at the first picture at this link on LVDS, you will see that LVDS, at its heart, is a 3.5 mA constant current supply that is switched via an 'H' bridge circuit so it actually, it IS a current system which is why you need the terminating resistor to get you the the Hi and Lo voltage levels that the RSPECL inputs expect. |
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