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| Low cost logic analyzer probe for Rigol MSO5000 EasyEDA project |
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| Gandalf_Sr:
Thanks for the plug :D Sir Gandalf_Sr! I've been knighted and I never knew! |
| S. Petrukhin:
Friends, did someone use a board of my design? Please write a review if you don't mind. |
| hydrabus:
Thanks for your work I have converted it from EasyEDA to KiCad 5.1.7-1 and done a cleanup and rerouting with match length for the signal D0 to 15 (I have done the schematic from scratch too) The good news is now all is available on KiCad for a version which should work up to 1GSPS (the limit of the MSO5000 LA/TI SN65LVDS1DBVRG4+cables/probes ...). I have changed some parts also to better parts. The big plus is I provide also the JLCPCB SMT script to convert the KiCad BOM/POS to JLCPCB SMT BOM & CPL (see JLCPCB_PCBA directory) The files are available here http://hydrabus.com/Logic_Analyzer_Probe_Rigol_MSO5000_v2_2_BVE_19Oct2020_KiCad.7z I have bought 2 unit with full assembly(except LDO and connectors which are not available) and 3 spare PCBs of that design and I'm waiting to receive them in few days |
| TurboTom:
Sorry for my ignorance, but I think it would be sufficient to keep the length of the sum of the individual input and output trace of each comparator equal, which would reduce the amount of wiggles and thus possible EMI and "pulse smearing" considerably. |
| S. Petrukhin:
--- Quote from: hydrabus on October 21, 2020, 11:42:19 am ---Thanks for your work I have converted it from EasyEDA to KiCad 5.1.7-1 and done a cleanup and rerouting with match length for the signal D0 to 15 (I have done the schematic from scratch too) The good news is now all is available on KiCad for a version which should work up to 1GSPS (the limit of the MSO5000 LA/TI SN65LVDS1DBVRG4+cables/probes ...). I have changed some parts also to better parts. The big plus is I provide also the JLCPCB SMT script to convert the KiCad BOM/POS to JLCPCB SMT BOM & CPL (see JLCPCB_PCBA directory) The files are available here http://hydrabus.com/Logic_Analyzer_Probe_Rigol_MSO5000_v2_2_BVE_19Oct2020_KiCad.7z I have bought 2 unit with full assembly(except LDO and connectors which are not available) and 3 spare PCBs of that design and I'm waiting to receive them in few days --- End quote --- You almost completely redesigne the trace, it was a lot of work to put so many wigglings. |O I also equalized the length of the output LVDS lines in the first version, but after I saw the photo of the scope board, I realized that this would not give privileges. The Chinese comrades did not even install a load resistor on the LVDS receiver side, let alone equalization differential lines. I'm not much of a high-frequency expert, but it seem like so much wiggling gives parasitic capacitance and inductance. I checked my version at 50 MHz later. The rectangular signal did not give jitter, the image is frozen. But the triangular signal showed a small jitter, probably a slight deviation in the switching level of the LVDS shapers inputs. It will be good if you create a project with your version on EasyEDA - it will be convenient for other people to make your version for themselves, which is important for high frequencies. |
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