Products > Test Equipment

Low cost logic analyzer probe for Rigol MSO5000 EasyEDA project

<< < (17/30) > >>

normi:
Got this built and was able to use it up 160MHz, there was jitter, but I have not worked out whether this could be improved with probing technique. Also I only had a few Dupont cables pieced together to use as probes. I used an FPGA which generated a 160MHZ clock then broke this into 4 bits which would count to 16, (0-F). The parallel decoder was used for this.
See attached screen shot.

normi:
Thanks to all who contributed to the design. :-+

S. Petrukhin:

--- Quote from: gurong60 on March 22, 2021, 01:49:26 pm ---Hello, why don't you use 4-layer PCB. JLC's 4-layer PCB is only 5 US dollars in size of 50*50mm. Size 100*100mm is only 9 US dollars.

--- End quote ---
It makes no sense to make 4 layers, fill two of them with a power bus and create parasitic capacities.  :)

S. Petrukhin:
I didn't use any stabilization tools for jitter. LVDS chips have a good slope of the output edge, and are quite good at determining the level at the input. But the probe lines introduce their own distortions. At a frequency of 160 MHz, this is already noticeable.

However, the observation by the logic probe of periodic signals in continuous mode (then where the jitter is observed) not really necessary. You can use analog channels for such purposes. I think digital inputs are more reasonable to use in packet capture mode with a sweep trigger in normal mode or a single shot.

moelski:
Hi !
Any chance to use this probe with my Rigol MSO1104Z ?

Dominik

Navigation

[0] Message Index

[#] Next page

[*] Previous page

There was an error while thanking
Thanking...
Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod