Low cost logic analyzer probe for Rigol MSO5000 EasyEDA project

[hydrabus]

I do not plan to do the work on EasyEDA as I do not know how it work and because everyone shall switch to a real EDA like KiCad as EasyEDA is clearly not good for advanced PCB and match length / high speed circuits...
For information the match length is here to avoid Clock skew with design v2.1 see https://en.wikipedia.org/wiki/Clock_skew for more details

The rule of thumb for High Speed differential signal (for 480MHz) is each member of a High-Speed differential pair should be no more than 1.25 mm (50 mil) longer than the other member.
If you check original design there was huge gap on match length see my document Signal_Length.ods:
1) Tuning Match Len Diff Signal DX+/- => Minimal trace was 11.18mm and max was 27.38mm so a delta of more than 16.2mm so it clearly violate the rule (>12 times) to do not exceed 1.25mm delta.
2) Tuning Match Len Signal DIX => Minimal trace was 14.16mm and Maximum trace was 75.98mm so a delta of more than 60mm
See reference https://blog.zuken.com/how-to-calculate-trace-length-from-time-delay-value-for-high-speed-signals/

• If you do the computation for a 400MHz it is just 3 times less than the example 1.2GHz so the signal you obtain a clock period of 2500ps with for striplines, the maximum skew should be less than +/-367.5 mil = 9.3345mm and here we have 60mm (>6 times more) ...
  
• If you do the computation for a 200MHz it is just 6 times less than the example 1.2GHz so the signal you obtain a clock period of 5000ps with for striplines, the maximum skew should be less than +/-735 mil = 18.669mm and here we have 60mm (>3 times more) ...
  
• If you do the computation for a 100MHz it is just 12 times less than the example 1.2GHz so the signal you obtain a clock period of 10000ps with for striplines, the maximum skew should be less than +/-1470 mil = 37.338mm and here we have 60mm (>1.6 times more) ...
  
• If you do the computation for a 50MHz it is just 24 times less than the example 1.2GHz so the signal you obtain a clock period of 20000ps with for striplines, the maximum skew should be less than +/-2940 mil = 74.676mm and here we have 60mm so it is ok but not with a big margin ...

An improvement to have less EMI/EMC and better differential routing... will be to use 4 Layers (1_Top, 2_GND, 3_PWR, 4_Bot).

About the questions:

Sorry for my ignorance, but I think it would be sufficient to keep the length of the sum of the individual input and output trace of each comparator equal, which would reduce the amount of wiggles and thus possible EMI and "pulse smearing" considerably.

It is mandatory to do match length on single ended and differential traces separately.
About possible EMI and "pulse smearing" see the paper "Differential Lines Paired with Serpentine as PotentialEMI Aggressors in Mobile Electronic Devices" https://sci-hub.se/https://ieeexplore.ieee.org/document/8114328
We clearly see in this paper EMI/EMC are a potential problem on multi GHz (but not for signal < 500MHz) which is not the case here as we cannot exceed 500MHz anyway with 1GSPS and in fact when you have added all limitations of hardware it will be probably limited to max 200 or 250MHz but the improvements with match length / serpentine + multi via to GND (to reduce EMI/EMC ...) remove the limitation of the original PCB which is limited to less than 100MHz signal and shall allow to capture up to 250MHz(or even up to 500MHz in theory) signal without clock skew issues.[/list]

[S. Petrukhin]

For information the match length is here to avoid Clock skew with design v2.1 see https://en.wikipedia.org/wiki/Clock_skew for more details

I have some knowledge in the alignment of the length of the lines. But all efforts are still leveled by the scope itself, where the length of the lines was not thought of. In addition, the bandwidth of the logic analyzer is limited and it does not reach the value you mentioned. I made a simple, very cheap option. This is by no means an accurate or calibration device. Most people don't need to take measurements at high frequencies. I don't have more than 50 MHz anywhere.

You've done some serious research. Your option is worthy of special attention for special cases for cool professionals, but they have a lot of money to buy an expensive scope and logic analyzer. 

[Gandalf_Sr]

I'm pretty sure that the LA probe on the MSO5000 series samples at 1 GHz so the absolute maximum frequency that could be sampled is reasonably about 400 MHz.  At 400 MHz, the wavelength in copper is around 700 mm.  Worrying about less than 2 mm trace length matching is pointless IMHO.

[S. Petrukhin]

I'm pretty sure that the LA probe on the MSO5000 series samples at 1 GHz so the absolute maximum frequency that could be sampled is reasonably about 400 MHz.  At 400 MHz, the wavelength in copper is around 700 mm.  Worrying about less than 2 mm trace length matching is pointless IMHO.

The Rigol MSO5074 specification states that the maximum LA frequency is 200 MHz. 

[Sharp]

@hydrabus and @Petrukhin

Thank you for your excellent work - very appreciated   

Are we now looking into two deterrent designs and two deferent tests ? or are you working together on this project ?

[Gandalf_Sr]

The Rigol MSO5074 specification states that the maximum LA frequency is 200 MHz. 

Yes, they are saying that they don't spec for logic clock frequencies higher than 200 MHz but you need at least double this as the sampling rate; again, I am pretty sure that the MSO5000 samples the LA pins at 1 GHz, that's why there's a 1 nS jitter when you're looking at 200 MHz waveforms.

[Gandalf_Sr]

@hydrabus and @Petrukhin

Thank you for your excellent work - very appreciated   

Are we now looking into two deterrent designs and two deferent tests ? or are you working together on this project ?

The 2 projects are both LA probe leads that plug into the Rigol MSO5000 series scopes but they are completely different designs.

Mine came first.  I have looked at S.Petrukhin's design and offered him my advice and what I believe is constructive criticism.  I am not running a business (at least not one selling LA probe PCBs) and I don't feel like I'm in competition here.

[EDIT] I now realize that you were asking about Hydrabus' design vs S.Petrukhin's.  I have a completely unrelated design here.

[S. Petrukhin]

@hydrabus and @Petrukhin

Thank you for your excellent work - very appreciated   

Are we now looking into two deterrent designs and two deferent tests ? or are you working together on this project ?

I quickly made a simple version myself which is easy to repeat by ordering PCB and accessories in a couple of clicks.. I was really helped by the guys in this forum, who studied and gave information about the standard device. @Gandalf_Sr especially helped-he found errors and suggested them to me. @hydrabus upgraded the board and made an independent version.

[simogi]

Good evening,
I just bought a rigol mso5000.
I came across this blog.
I went to the Chinese site:
https://easyeda.com/f33net/digital-probe-rigol-mso5000

I saw an opportunity to purchase components.
But I don't see an opportunity to buy the board.

I know it's a simple question but can you help me?

Simogi

[S. Petrukhin]

Good evening,
I just bought a rigol mso5000.
I came across this blog.
I went to the Chinese site:
https://easyeda.com/f33net/digital-probe-rigol-mso5000

I saw an opportunity to purchase components.
But I don't see an opportunity to buy the board.

I know it's a simple question but can you help me?

Simogi

Hi!

I answered you on that site: you need to open the PCB in the Editor (see this name button) and select [Fabrication / PCB Fabrication file (PCB)] from the menu there. Then choose when ordering 5 pieces - they will cost $2 plus shipping.

[simogi]

Thanks so much for the reply.

Now I have succeeded.

I saw in the BOM (components list) that the connectors and flat cable between rigol and board are missing. Do you know them or do you know where I can get a pre-made cable?

Thanks again

Simone G. O.

[S. Petrukhin]

Thanks so much for the reply.

Now I have succeeded.

I saw in the BOM (components list) that the connectors and flat cable between rigol and board are missing. Do you know them or do you know where I can get a pre-made cable?

Thanks again

Simone G. O.

Use it for your fun. 

I had connectors for the wire and the wire itself, I bought them in advance. These are simple items that you can buy at a local store. I didn't search for them on LCSC. Here are the links to Aliexpress that I used to buy:

Pogo pin P100-F1: https://aliexpress.com/item/4001365760976.html
Dupon socet for pins: https://aliexpress.com/item/32717763865.html
Single cable 28 AWG 5 meters for pins: https://aliexpress.com/item/4000009001537.html
Test clips: https://aliexpress.com/item/4000550690107.html
Test clips: https://aliexpress.com/item/4000340698351.html
Flat cable 50 wire: https://aliexpress.com/item/32946950330.html
Socet for flat cabble 50 pin: https://aliexpress.com/item/4000114961257.html

[simogi]

I took it all,

Now I have everything to start.

Thanks

Simone G. O.

[calippo]

Any feedbacks?
As Kicad user, I was planning to pursue the JLCPCB option too. 

Thanks for your work
I have converted it from EasyEDA to KiCad 5.1.7-1 and done a cleanup and rerouting with match length for the signal D0 to 15 (I have done the schematic from scratch too)
The good news is now all is available on KiCad for a version which should work up to 1GSPS (the limit of the MSO5000 LA/TI SN65LVDS1DBVRG4+cables/probes ...).
I have changed some parts also to better parts.
The big plus is I provide also the JLCPCB SMT script to convert the KiCad BOM/POS to JLCPCB SMT BOM & CPL (see JLCPCB_PCBA directory)

The files are available here http://hydrabus.com/Logic_Analyzer_Probe_Rigol_MSO5000_v2_2_BVE_19Oct2020_KiCad.7z
I have bought 2 unit with full assembly(except LDO and connectors which are not available) and 3 spare PCBs of that design and I'm waiting to receive them in few days

[nullik]

Any feedbacks?
As Kicad user, I was planning to pursue the JLCPCB option too. 

I checked design in KiCad and think all fine. Also I got my PCBs with this design.
Now I waiting electronic componets for checking device.
After I get the EC and check device, I will write the results here.
The design is not perfect and can still optimize pcb.
I will check the delay in differential pairs, if i found mistakes then I make my own PCB.

[S. Petrukhin]

Any feedbacks?
As Kicad user, I was planning to pursue the JLCPCB option too. 

I checked design in KiCad and think all fine. Also I got my PCBs with this design.
Now I waiting electronic componets for checking device.
After I get the EC and check device, I will write the results here.
The design is not perfect and can still optimize pcb.
I will check the delay in differential pairs, if i found mistakes then I make my own PCB.

It looks like you used the hydrabus design. As discussed here, and according to the results of my tests, its changes will not interfere with the work, but for the bandwidth of LA MSO5074 they are not it does not matter.

[nullik]

It looks like you used the hydrabus design. As discussed here, and according to the results of my tests, its changes will not interfere with the work, but for the bandwidth of LA MSO5074 they are not it does not matter.

Yes, I use his design. Perhaps you are right. But I know strict requirements high freq designs like USB bus.
Differential pairs work only if they have the same delay. And they become very easily ineffective if this rule is violated.
A simple example of a USB bus, with bad cable it can work ustable, lose
synchronization, data transfer speed drops.
The correct way is not to align the length of the lines, the correct is to align their delays.
Also for a better high freq design and low noise, you need to have at least a 4-layer PCB.
At high frequencies, we are very dependent on reactive capacitances and inductances.

[S. Petrukhin]

It looks like you used the hydrabus design. As discussed here, and according to the results of my tests, its changes will not interfere with the work, but for the bandwidth of LA MSO5074 they are not it does not matter.

Yes, I use his design. Perhaps you are right. But I know strict requirements high freq designs like USB bus.
Differential pairs work only if they have the same delay. And they become very easily ineffective if this rule is violated.
A simple example of a USB bus, with bad cable it can work ustable, lose
synchronization, data transfer speed drops.
The correct way is not to align the length of the lines, the correct is to align their delays.
Also for a better high freq design and low noise, you need to have at least a 4-layer PCB.
At high frequencies, we are very dependent on reactive capacitances and inductances.

This has already been discussed. Rigol engineers did not even bother to install load resistors on the receiver side and did not turn them on inside the FPGA, and you will worry about leveling a couple of centimeters of the track. It's like covering up the gold of the thatched roofs. 
You create more inductance and capacitance by looping the track.

[nullik]

I checked KiCad logic probe. All works fine.
I gave my pcb to people. I will be making the next version of the probe with a different plug on the output so that I can use high frequency shielded wires from dslogic.

https://www.dreamsourcelab.com/shop/accessories/shielded-fly-wires/

[S. Petrukhin]

I checked KiCad logic probe. All works fine.
I gave my pcb to people. I will be making the next version of the probe with a different plug on the output so that I can use high frequency shielded wires from dslogic.

https://www.dreamsourcelab.com/shop/accessories/shielded-fly-wires/

Shielded doesn't mean high-frequency. High-frequency lines must be matched.

And for shielded wires, you can use double female pin, because each input has its own personal Gnd pin in an existing connector. 
Get a savings of 23 bucks.

[S. Petrukhin]

By the way, the LVDS chip is very small. For complex environments where there are requirements for protection against interference, it is possible to embed this chip directly into the tip of the probe and transmit a stable LVDS signal directly from the spot.

[yelworc]

I was on the hunt for nice probes to go with this,

Dream source seems to be a good bet.
https://www.dreamsourcelab.com/shop/accessories/shielded-fly-wires/

I'll let you know about the compatibility

There's also these if you want dirt cheap
https://www.aliexpress.com/item/33060152163.html?spm=a2g0o.productlist.0.0.350bd45aRmKXPk&algo_pvid=6ace0999-564b-4c96-a24d-4ea97aea9a24&algo_expid=6ace0999-564b-4c96-a24d-4ea97aea9a24-26&btsid=0bb0624116145943214698372e4b06&ws_ab_test=searchweb0_0,searchweb201602_,searchweb201603_

[S. Petrukhin]

I was on the hunt for nice probes to go with this,

Dream source seems to be a good bet.
https://www.dreamsourcelab.com/shop/accessories/shielded-fly-wires/

I'll let you know about the compatibility

There's also these if you want dirt cheap
https://www.aliexpress.com/item/33060152163.html?spm=a2g0o.productlist.0.0.350bd45aRmKXPk&algo_pvid=6ace0999-564b-4c96-a24d-4ea97aea9a24&algo_expid=6ace0999-564b-4c96-a24d-4ea97aea9a24-26&btsid=0bb0624116145943214698372e4b06&ws_ab_test=searchweb0_0,searchweb201602_,searchweb201603_

Here published a list of the materials I used: https://www.eevblog.com/forum/testgear/low-cost-logic-analyzer-probe-for-rigol-mso5000-easyeda-project/msg3344750/#msg3344750

I made myself tails for the probes from thin silicone wires very soft. The probes you found on Aliexpress use an ordinary PVC wire that is very hard.

[justanothername]

I ordered the PCBS of this they came today.  Thank you for this.
Two remarks:
Firstly the groundplane is only on bottom and hatched. There is no technical reason to make it hatched. Better use a solid plane on both sides.
Secondly, and this is way more relevant, the plane is not connected to the probe ground. It is floating. That is not a good idea in my opinion. Better connect it to GND or do not use a plane at all.
This weekend is assembly time and testing.

[S. Petrukhin]

This is a two-layer board, there is no free layer for solid fill.

Using a grid in a polygon is just as good for shielding and removing static electricity as a solid fill, but the grid has many times less capacity to the tracks.

However, it is not a shielding layer and it is not connected directly to the Gnd, but neen connext to PE, because its task is to remove static charges, it is connected via the resistor R18 and the capacitor C5.
I chose bad nominals just to avoid creating new positions in BOOM, But this is not essential. It is best to use a 1MOm resistor and a 100pF high-voltage capacitor there.

If you wish, you can close R18 and get a grid rigidly attached to Gnd.