I do not plan to do the work on EasyEDA as I do not know how it work and because everyone shall switch to a real EDA like KiCad as EasyEDA is clearly not good for advanced PCB and match length / high speed circuits...

For information the match length is here to avoid Clock skew with design v2.1 see

https://en.wikipedia.org/wiki/Clock_skew for more details

The rule of thumb for High Speed differential signal (for 480MHz) is each member of a High-Speed differential pair should be no more than 1.25 mm (50 mil) longer than the other member.

If you check original design there was huge gap on match length see my document Signal_Length.ods:

1) Tuning Match Len Diff Signal DX+/- => Minimal trace was 11.18mm and max was 27.38mm so a delta of more than 16.2mm so it clearly violate the rule (>12 times) to do not exceed 1.25mm delta.

2) Tuning Match Len Signal DIX => Minimal trace was 14.16mm and Maximum trace was 75.98mm so a delta of more than 60mm

See reference

https://blog.zuken.com/how-to-calculate-trace-length-from-time-delay-value-for-high-speed-signals/- If you do the computation for a 400MHz it is just 3 times less than the example 1.2GHz so the signal you obtain a clock period of 2500ps with for striplines, the maximum skew should be less than +/-367.5 mil = 9.3345mm and here we have 60mm (>6 times more) ...

- If you do the computation for a 200MHz it is just 6 times less than the example 1.2GHz so the signal you obtain a clock period of 5000ps with for striplines, the maximum skew should be less than +/-735 mil = 18.669mm and here we have 60mm (>3 times more) ...

- If you do the computation for a 100MHz it is just 12 times less than the example 1.2GHz so the signal you obtain a clock period of 10000ps with for striplines, the maximum skew should be less than +/-1470 mil = 37.338mm and here we have 60mm (>1.6 times more) ...

- If you do the computation for a 50MHz it is just 24 times less than the example 1.2GHz so the signal you obtain a clock period of 20000ps with for striplines, the maximum skew should be less than +/-2940 mil = 74.676mm and here we have 60mm so it is ok but not with a big margin ...

An improvement to have less EMI/EMC and better differential routing... will be to use 4 Layers (1_Top, 2_GND, 3_PWR, 4_Bot).

About the questions:

Sorry for my ignorance, but I think it would be sufficient to keep the length of the sum of the individual input and output trace of each comparator equal, which would reduce the amount of wiggles and thus possible EMI and "pulse smearing" considerably.

It is mandatory to do match length on single ended and differential traces separately.

About possible EMI and "pulse smearing" see the paper "Differential Lines Paired with Serpentine as PotentialEMI Aggressors in Mobile Electronic Devices"

https://sci-hub.se/https://ieeexplore.ieee.org/document/8114328We clearly see in this paper EMI/EMC are a potential problem on multi GHz (but not for signal < 500MHz) which is not the case here as we cannot exceed 500MHz anyway with 1GSPS and in fact when you have added all limitations of hardware it will be probably limited to max 200 or 250MHz but the improvements with match length / serpentine + multi via to GND (to reduce EMI/EMC ...) remove the limitation of the original PCB which is limited to less than 100MHz signal and shall allow to capture up to 250MHz(or even up to 500MHz in theory) signal without clock skew issues.[/list]