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| MS05000 Budget Logic Analyzer Probe Set Design |
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| Gandalf_Sr:
While the vn 1a boards seem to work just fine, I have a tweak in progress to fix very minor issues, like the adjustable voltage control pot works backwards. I have a few other tweaks to consider too. If I order new vn 1b PCBs I can add to the order if anyone's interested? PM me if you want a set. I'll update the schematics and add the BOM later this week. |
| thmjpr:
--- Quote from: Gandalf_Sr on March 14, 2020, 08:00:59 pm ---Here's an picture of the connector PCB (before I added all the termination resistors). [EDIT] Did some high frequency tests on the 0.65-3.6V probe PCB running at 3.3V with a 50 MHz square wave from my DG4202; it looked OK but there was an occasional 1 nS jitter on all channels. I wonder if that was the signal generator? --- End quote --- Nice work. You can see in the specs the LA sample rate is 1Gs/s, so 1ns jitter may be expected. |
| Gandalf_Sr:
--- Quote from: thmjpr on March 16, 2020, 09:28:30 pm --- --- Quote from: Gandalf_Sr on March 14, 2020, 08:00:59 pm ---Here's an picture of the connector PCB (before I added all the termination resistors). [EDIT] Did some high frequency tests on the 0.65-3.6V probe PCB running at 3.3V with a 50 MHz square wave from my DG4202; it looked OK but there was an occasional 1 nS jitter on all channels. I wonder if that was the signal generator? --- End quote --- Nice work. You can see in the specs the LA sample rate is 1Gs/s, so 1ns jitter may be expected. --- End quote --- Thanks, so that suggests that the jitter is not a problem of my design :) In reality, there are not many serial data systems that I've designed that run at more than a few MHz so this is likely a non-issue. My aim was to make it cheap and functional and I think I achieved that. One thing I haven't found yet is where in the menus I can align the analog and digital signals in time - I thought that was somewhere in the menus? |
| NoisyBoy:
Nice, love reading all the great progresses you are making. |
| Gandalf_Sr:
Question on Front End Protection So the probe design is working fine at 50 MHz but I had originally designed in some protection on the front end (see picture). J1 is the probe input connector and R0-R7 are 200 \$\Omega\$ series resistors and the results I've posted so far are just with those series resistors fitted. The 3.6V dual Zeners (D2-D5) arrived yesterday and I fitted them but they clearly affect a 10 MHz 3V square wave so they are not going to work and I took them off. I tried adding terminator resistors R13-R20 but they don't seem to have any affect at all and a TI engineer on the e2e forum thought I didn't need them. However, the datasheet for the SN74AXC8T245 warns that it shouldn't have floating inputs but the chip seems just fine with just the series resistors and, with nothing connected, the detected level registers as a zero. I have various FET scope probes that have warnings about maximum voltage. The schematic shown is for the 3.3V probe version (the 5V version uses an SN74LVC8T245 as U3) and the absolute max input voltage for the SN74AXC8T245 is 4.2V according to the DS so a 5V logic input could fry it (with the LVC version it's 6.5V but the minimum Vcca voltage is limited to 1.65V). I don't work with 5V logic but I did build a probe PCB that has the 74LVC part in case I ever needed to. Before I tweak and make V1b of the probe PCBs, what do you guys think I should have at the front end? 1. Just the series resistors and provision for the termination resistors on the PCB so people can populate if they want - you fry it, you change U3. 2. Option 1 but with series and termination resistors fitted - might offer some protection but changes input impedance to 10k \$\Omega\$ 3. Something else??? |
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