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MS05000 Budget Logic Analyzer Probe Set Design

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Gandalf_Sr:
Design Aim
The design aim is for a budget LA probe for the MSO5000 that can be built to work in 2 positive voltage ranges:

1. 0.65V - 3.6V logic levels using a SN74AXC8T245 as U3 on the probe PCB - probably at 100 MHz or more (to be tested) but tested at 50 MHz.
2. 1.6V - 5.5V logic levels using a SN74LVC8T245 as U3 on the probe PCB (and other minor component differences) - tested at 50 MHz.

The official Rigol connector (PLA2216) uses expensive Op Amp ICs that can (theoretically) work up to 15V and 1GHz but they cost $400 a set ($350 if bought with the scope) and the scope LA input is only specified up to 200 MHz.

Project Status
The design is finished, the 3.3V version of the probe PCB has been built and tested at 50 MHz. I have ordered a load of PCBs so if you want a set, look at this post and PM me with what you need.  Then go and check out this post that has links to Digikey carts that will allow you to buy all the parts needed. The schematics in .pdf an BOM in Excel are here.

High Level Summary
The design uses 2 different PCBs:
1. A passive (no active components) Connector PCB that adapts from the MSO's 50-pin 0.1" header (J1) to 2 x 0.1" pitch 24-pin headers that take standard ribbon cables.
2. Two Probe Adapter PCBs that convert the sensed logic signals into LVDS which they drive into the ribbon cables.

Each probe PCB has an 8 bit voltage level translator (VLT) IC followed by 2 x 4 bit LVDS driver ICs.  The LVDS driver ICs and the output (B) side of the VLT run at 3.3V which is supplied by a 3.3V, 300 mA LDO regulator (that supply is also available for your use on the 3.3V test pin).  The input (A) side of the VLT is powered from an adjustable 0.6V to 3.9V, 100 mA LDO regulator (that supply is also available for your use on the Vadj test pin).


Probe Adapter PCB
This description is for the 0.65-3.6V version (with the 1.6-5.5V version differences shown in parentheses); the 3.3V LVDS signals these boards output are the same and any combination of probe PCBs can be attached to the Connector PCB.
Eight logic sensing leads connect to J1 feed into the A side of a SN74AXC8T245 (SN74LVC8T245) which is an 8-bit voltage level translator (VLT) that can range from 0.65 to 3.6V (1.6 to 5.5V) operating voltage. The VLT is hard-wired to make the A side the input and the B side th eoutput.  The outputs on the B side of the VLT run at 3.3V and feed a pair of DS90LV047A LDVS driver ICs that drive the LVDS signals to the Connector PCB via the 24-pin header connectors and ribbon cable.

There are 2 separate power supplies on the Probe PCB both fed by the 4V line passed from the Connector PCB:
1. A 300 mA 3.3V fixed LDO linear regulator that supplies the DS90LV047A LDVS drivers and VccB on the SN74AXC8T245 (SN74LVC8T245).
2. A 100 mA LDO that is adjustable from 0.65 to 3.6V which supplies Vadj.

A switch selects what voltage is fed to the VccA side of the VLT IC, U3; it selects between Vadj or Vext (an external voltage that you have to feed in on a pin on J1).  This allows the device under test (DUT) to be powered by Vadj up to 100 mA (the level translator IC uses uAs) or for the DUT to provide the power to VccA. The max voltage that should be fed into the Vext pin is 3.6V (5.5V) but a protection Zener diode protects the SN74xxx8T245 VccA side.  To monitor logic at voltages greater than 3.6V on the SN74LVC8T245, VccA must be sourced from the Vext pin because the Vadj supply only goes up to 3.6V (YMMV but the limit is the actual 4V level from the scope and the drop over the LDO regulator).  Note that the level adjustments available on the MSO5000 menus don't do anything as the input resolution of a 1 or 0 is related to the VccA applied to U3.

The Probe PCBs are only 2 layer; I ran impedance calculations for the 2-layer PCB and it comes out around 130 \$\Omega\$ for 1.6mm FR4 and my trace widths so I think it will be OK up to 100 MHz or so.

200 \$\Omega\$ series resistors (R0-R7) provide basic protection to the inputs to the SN74AXC8T245 and there are also optional 10k \$\Omega\$ load resistors (R13 - R20) on each input. Care should be taken not to overvolt the inputs or U3 could be damaged.

The Connector PCB
This is 4-layer passive circuit that routes the LVDS signals coming from the Probe PCBs to the front connector on the MSO5000. The pairs of LVDS signals are length matched to <3mm and the channels are all within 10 mm of each other. The traces have been moved to be on the same side for each LVDS pair (as far as possible) and have curved traces to avoid reflections (all probably overkill for 100 MHz).

The latest schematics are attached to this post.

[Edit1] Upload of .pdfs schematics
[Edit2] 2/28/20 to reflect 5V option and protection components
[EDIT3] 3/8/2020 major update of all text to reflect design changes and build status
[EDIT4] 3/14/2020 first & second posts updated to show working status and pictures of it running
[EDIT5] 3/21/2020 updated to reflect the choices made for input protection on Probe/Connector vn1b2/1a4 PCBs
[EDIT6] 3/23/2020 updated to delete the schematics attached to this post and point to the latest ones
[EDIT7] 3/28/2020 added more detail to the circuit description
[EDIT7] 4/28/20 added link to post that has zipped schematics and BOM
[EDIT8] 5/2/20 changed VccIO to Vext to match markings on Probe PCB
[EDIT9] 5/21/20 minor changes to enhance readability and clarity

thmjpr:

--- Quote ---maximum logic level voltage of 3.6V (4.2 absolute max)
--- End quote ---
]

If you are saying it will be damaged when going above 4.2V, I would consider adding some resistor protection. At least to prevent the thing from being blown up, if you inadvertently touch the probe to a 5V rail say.

I would say enjoy the cruise, but yeah this is probably more interesting for you :D

Gandalf_Sr:
[EDIT] Here are the pictures of the finished 3.3V version running at 10 MHz.

Gandalf_Sr:

--- Quote from: thmjpr on February 26, 2020, 11:09:35 pm ---
--- Quote ---maximum logic level voltage of 3.6V (4.2 absolute max)
--- End quote ---
]

If you are saying it will be damaged when going above 4.2V, I would consider adding some resistor protection. At least to prevent the thing from being blown up, if you inadvertently touch the probe to a 5V rail say.

I would say enjoy the cruise, but yeah this is probably more interesting for you :D

--- End quote ---
It's ages since I looked at any 5V logic.  The issue I have run into recently is being able to handle sub 3.3V logic levels, this setup goes all the way down to Vcc at 0.65V.  Adding a simple voltage divider to deal with 5V logic should be very simple.

[EDIT} Keep reading as the design was enhanced to allow use of a LVC VLT IC to handle up to 5.5V logic levels.

texaspyro:

--- Quote from: Gandalf_Sr on February 27, 2020, 02:57:07 am ---It's ages since I looked at any 5V logic.

--- End quote ---

Supporting 5V levels wou;d be a very good thing (I'd consider essential for any logic analyzer).  There is a LOT of older 5V equipment (and Arduinos) out there that need an occasional probing.

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