Products > Test Equipment
New bench scope - Fnirsi 1014D, 7", 1GSa/s
pcprogrammer:
--- Quote from: MrAl on November 24, 2022, 06:37:00 am ---Oh geeze, that must have been one hell of an undertaking, how did you do that? Did you have to follow all the traces around the boards?
--- End quote ---
With the use of a digital multi meter and pictures it is not that big an undertaking. Reverse engineering the software and the FPGA, those are the real undertakings. The software for the 1013D took about a year (not full time of course) to get from the first disassembly / de-compile to newly written functioning firmware. The FPGA took at least 6 months to get from almost zero to a full understanding on what it is made up with.
Wrote about it here: https://www.eevblog.com/forum/fpga/reverse-engineering-anlogic-al3_10-fpga/
chupocro:
I wonder if anyone designed a convenient circuit that could be connected to 1014D's function generator and would be used for adjusting the amplitude.
Maybe an emitter follower not to overload the output followed by non-inverting adjustable amplifier using op-amp(s). Gain should be adjustable from less than 1.0 to some max value (e.g. 12 V).
chupocro:
I tested it with an old circuit I made a few years ago for experimenting with DDS sound synthesis.
ATmega8 @ 8 MHz internal oscillator is generating 15686.27 Hz PWM signal while interrupt routine running at the same frequency is used to adjust duty cycle.
https://youtu.be/n-j5uSacw70
donwulff:
Spectacular work with the reverse-engineered firmware! I've been wondering though, given this is the FNIRSI 1014D thread, what are the chances of building open-source firmware for the 1014D as well? it sounds like their hardware is very similar, save for the signal generator? For the price it might be a nice platform to perhaps try some simple signal processing/UI improvements. Maybe I should start with some of the tear-down comparisons of the two models people were referring to?
Also about the true performance. If I understand right both probes have two-channel 100 megasample 8 bit ADC:s? So if the FPGA is indeed driving this at 100 megasamples (And I see the datasheet might have little leeway to increase that higher, maybe?) that would be 2x200 megasamples at 7.5bit? 3nS rise-time spec would mean 6 times oversampling, but I guess the real rise-time is more like 10nS? The 1 Gs/s, while made up, is close to the combined analog bandwidth, so I guess if you knew the waveform and/or it was repeating, you could interpolate up to that? ~200Mhz sine-wave? Then again I suppose they're already using a lot of those tricks.
Basically wondering what the actual specs & capabilities are, derived from the firmware, and if the stock firmware is already using those to the max. Still could benefit from things like stacked & fading traces, trace differences etc.
py-bb:
What's the 100mhz @ 1Gsample/sec mean? Surely that'd be 500mhz(ish) scope? Or is it combining 5 samples into 1 to use a shitty DAC for better dynamic range?
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