I found this on a Xilinx website with some funny chinese URL.
SDS1000X-E - SIGLENT A new generation of entry -level oscilloscopes based on the ZYNQ platform
Modified by junweiz Modified on 01-19-2017 06:18 PM (95 Views) 2017-01-19 Ding Yang Technology
Overview
In November 2016, SIGLENT released a new generation of entry-level oscilloscope SDS1000X-E, its maximum bandwidth of 200 MHz, sampling rate of 1 GSa / s, standard storage depth of 14 M points; it is worth mentioning that, SIGLENT will only before The SPO Super Fluorescent Digital Oscilloscope technology, which is used in high-end series oscilloscopes, is integrated into this entry-level product with a high sensitivity, low-triggering digital triggering system, up to 400,000 frames per second waveform capture rate and 256 levels of brightness level display; the SDS1000X-E also supports a wealth of data acquisition and processing functions, including intelligent triggering, serial bus triggering and decoding, historical mode and sequence mode, rich measurement and math Operations, up to 1M points of the FFT, etc., redefine the entry-level oscilloscope.
Can be some of the high-end digital oscilloscope only with the indicators and functions reflected in the entry-level oscilloscope, thanks to SIGLENT in SDS10 00X-E using Xilinx Zynq-7000 SoC as the core processing chip.
? Figure 1 SDS1000X-E integrated Zynq-7000
The XC7Z020 SoC chip used in the SDS1000X-E has a dual-core ARM Cortex-A9 processor (PS) + Artix-7 architecture based FPGA (PL), where the processor supports up to 866 MHz and the FPGA part 85k logic unit, 4.9 Mb block RAM and 220 DSP slices, and provides support for common external memory such as DDR2 / DDR3, which is very suitable for data acquisition, storage and digital signal processing in digital oscilloscopes . At the same time, Zynq-7000 PS (processor system) and PL (programmable logic) part of the interconnection between the AXI high-speed bus , can effectively solve the traditional digital storage oscilloscope CPU and FPGA data transmission between the bandwidth bottlenecks , Which helps to reduce the dead time of digital oscilloscope and improve the waveform capture rate. Replacing traditional CPU + FPGA discrete solutions with monolithic SoC chips also reduces hardware footprint and facilitates integration of high performance processing systems into compact entry-level oscilloscopes.
Data collection and storage
Figure 2 SPO engine with Zynq-7000 architecture
The high-speed analog-to-digital converter (ADC) chip used in the SDS1000X-E has a data interface of LVDS differential pair, with a rate of 1 Gbps per pair of LVD S. Using the Zynq-7000 chip, the programmable IO LVDS maximum rate of up to 1.25 Gbps, can guarantee a stable and reliable access to the ADC to the data.
At the same time, FPGA received high-speed ADC data needs to be written to the memory in real time, 8-bit, 1 GSa / s ADC, for example, the output data throughput of 1 GByte / s. Zynq-7000 supports commonly used DDR2, DDR3 and other low-cost storage, the highest DDR3 interface rate of up to 1066 MT / s, so the use of single-chip DDR3 to meet the real-time storage of the ADC output data requirements. Moreover, Zynq-7000 supports PL shared PS memory, as long as the PS part of the reserved memory bandwidth, the remaining bandwidth for storing ADC data, no need to re-plug in the PL part of the memory, reducing costs.
More importantly, based on the Zynq-7000's rich programmable logic resources (XK7Z020 for the 85k equivalent logic unit), SDS1000X-E integrated high sensitivity, low jitter, zero temperature drift digital trigger system, making it trigger more For the accurate; all kinds of intelligent trigger functions such as slope, pulse width, video, timeout, rungs, pattern, etc., can help users more accurately isolate the waveform of interest; bus protocol trigger or even directly with the conditions of the bus event (Such as the start of the I2C bus, or UART-specific data) as a trigger condition, greatly facilitate debugging.
? Figure 3 analog trigger system and digital trigger system trigger jitter contrast
Data interaction
With the increase of the complexity of digital oscilloscope design and the improvement of processor processing capacity, the bus structure is becoming the bottleneck of system performance. The traditional entry-level digital oscilloscope, using low-cost embedded processor as the control and processing core, using low-cost FPGA to achieve data acquisition and storage, the two through the parallel local bus interconnection, the processor as a master device , FPGA as a slave device; bus also connected to other processor peripherals, such as F LASH, USB controller, as shown in Figure 4.
? Figure 4 Traditional architecture of the embedded processor and FPGA interconnection
The biggest problem with this interconnection is that the data throughput is low, first because the local bus is typically an asynchronous bus, ideally a read / write access takes at least 3 cycles (1 setup cycle, 1 access cycle and 1 Hold period). With a 16-bit wide, external bus frequency of 100 MHz local bus, for example, the ideal maximum bus access throughput of 66 MB / s; the second is because the read and write operations share a set of addresses, data bus, ; Third is that multiple slave devices will compete for the bus, thereby reducing the effective data throughput for each slave device. Taking a digital oscilloscope with a sampling rate of 1 GSa / s as an example, the time taken to sample 10 M points is only 10 ms, but the time to transmit 10 M points (at an ideal 66 MB / s bus throughput rate) is at least 150 ms, 15 times the data sampling time. In other words, even if the data processing time is not taken into account, the dead time has reached 15/16 = 93.75%.
The SDS1000X-E adopts the Zynq SoC architecture. The high-speed AXI bus interconnection between the processor (PS) and the FPGA (PL) can effectively solve the bandwidth bottleneck problem of data transmission between the two , greatly improving the data throughput and reducing the number of oscilloscope Dead time. Zynq-7000 used in the four AXI-HP port, each port supports a maximum 64-bit wide, up to 250 MHz clock frequency; while reading and writing channels are separated, can perform full-duplex operation; PS and PL between Point-to-point transmission, there is no bus with other devices to compete. Using a single HP port to transmit data, the throughput rate can easily reach the two-way 1 GB / s speed, 4 ports can achieve a total of read and write rates of more than 8 GB / s, far greater than the local bus transmission rate.
? Figure 5 Zynq SoC in the processor and programmable logic interconnect
Digital signal processing
The SDS1000X-E is equipped with a number of high-performance, powerful digital signal processing functions such as FFT support for 1 M point operation, enhanced resolution (Eres), 14 M full sampling point serial protocol decoding, 14 M full sampling Point of a variety of measurements and mathematical operations, etc., greatly improving the entry-level digital oscilloscope digital signal processing capabilities.
Zynq-7000 rich hardware resources for the SDS1000X-E digital signal processing functions provide a strong support. The XC7Z020 SoC chip used in the SDS1000X-E has a dual-core ARM Cortex-A9 processor with a maximum clock speed of 866 MHz. The parallel coprocessor NEON can perform digital signal processing at the software level. The PL section has 220 DSP slices And 4.9 Mb block RAM; coupled with high throughput between the PS and PL data interfaces, we have the flexibility to configure different hardware resources for different digital signal processing.
Operation instructions are complex, suitable for software implementation functions, can be achieved in the PS side, such as the signal rising edge of the measurement; need to use a large number of cumulative operation, the higher the dependence on hardware resources, can be achieved in the PL side, such as oscilloscope Common interpolation filters.
Some complex functions, you can use the PS and PL between the high data bandwidth for co-processing, such as FFT operations, in the PL side using rich DSP Slice and block RAM resources to build the coprocessor basic FFT operation hardware acceleration, PS Side to achieve a complex window function calculation, drawing, UI and other operations. Based on this co-processing architecture, the FFT on the SDS1000X-E supports up to 1M points of FFT, while achieving very high spectral resolution, but also greatly speed up the refresh rate of the spectrum. Figure 6 shows the spectral resolution comparison at 16 k and 1 M points on SDS 1000X-E, respectively. In this example, we enter a two-tone signal for the oscilloscope with a frequency of 100 MHz and 100.05 MHz. We can not tell two sinusoidal signals so close from the spectrum obtained from the 16 k FFT. The signal is displayed as a frequency And the 1 M-point FFT spectrum has a significantly more detailed spectrum and signal processing gain, from the level of 100 times the expansion of the figure can be seen, two from 50 kHz sinusoidal models can be well separated.
? Figure 6 1M point FFT to obtain very high spectral resolution
Similarly, there are many such high-performance digital signal processing in the SDS1000X-E where many of these PS and PL are co-processed with each other. For example, the SDS1000X-E can perform a variety of measurements and serial protocol decoding of 14 M full sampling points , which are not available in many , mid-range oscilloscopes. Figure 7, the upper two figures for a mainstream midrange oscilloscope on the 10 ns rising edge of the measurement results, the bottom two pictures for the SDS1000X-E on the same signal measurement results. Can be seen in the hour base, the two measurements are more accurate, and the actual rise time difference, but in the big time base, the upper right shows the oscilloscope in 100 us / div can only display "<48ns "Note that at this time its original sampling rate is still 1 GSa / s, which shows that it is not the original measurement of the original waveform data, but after compression mapped to the data on the screen. The lower right shows the measurement result of the S DS1000X-E at 1 ms / div. Note that the sampling rate at this time is also 1 GSa / s, but the measurement accuracy is still 1 ns and can be more truly reflected Signal parameters.
SDS1000X-E digital signal processing based on full sampling points and up to 14 M points of storage depth, allowing users to observe the signal at the same time as a whole at the same time, still can get the details of the processing results; at the same time because of its Zy nq architecture Processing, making the signal processing performance and speed to achieve the best, with better real-time and flexibility.
? Figure 7 Compression point measurement and full sampling point measurement accuracy comparison
About SDS1000X-E
SIGLENT SDS1000X-E series of super fluorescent oscilloscope, with 70M, 100MHz and 200MHz bandwidth models, the sampling rate of 1 GSa / s, standard storage depth of 14 Mpts, the most commonly used features are user-friendly one-button design; using SPO technology , With excellent signal fidelity: the bottom noise is lower than the industry similar products, the smallest range of only 500 ?V / div; innovative digital trigger system, trigger high sensitivity, trigger jitter small; waveform capture rate up to 400,000 frames / sec (Sequence mode ), With 256 levels of brightness and color temperature display; support for a wealth of intelligent trigger, serial bus trigger and decoding; support history mode (History), sequence mode (Sequence) and enhanced resolution mode (Eres); rich Measurement and mathematical functions; 1M point FFT can be very detailed frequency resolution; 14M full sampling point measurement to ensure that the measurement accuracy and sampling accuracy of the same, no distortion; is a high-performance economic general-purpose oscilloscope.
About Zynq-7000
The Xilinx Zynq®-7000 Fully Programmable SoC (AP SoC) family of integrated ARM® processor software programmability and FPGA hardware programmability not only enables significant analysis and hardware acceleration, but also a highly integrated CPU on a single device , DSP, ASSP, and mixed-signal functions. The Zynq-7000 device is equipped with a dual-core ARM Cortex-A9 processor, which integrates with programmable logic based on 28nm Artix-7 or Kintex®-7 for superior performance-to-power ratio and maximum design flexibility.
About the AXI bus
AXI (Advanced eXtensible Interface) is a bus protocol, which is the most important part of ARM's AMBA (Advanced Microcontroller Bus Architecture) protocol. It is a high-performance, high-bandwidth, low-delay on-chip bus. Its address / control and data phases are separate, support for misaligned data transfers , while in burst transmissions only need to be the first address, while separating the read and write data channels and support Outstanding transmission access and outbound access, and Easier timing closure. AXI is a new high-performance protocol in AMBA. AXI technology enriches the existing AMBA standard content to meet the needs of ultra-high performance and complex system-on-chip (SoC) designs.
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