| Products > Test Equipment |
| Unknown GPSDO but BG7TBL logo on the circuit board and OCXO ! |
| << < (14/21) > >> |
| Hans_18T:
No, the GPS receiver in use provides a PPS, not a 10KHz output, so a PLL solution isn't "workable". |
| 0xFFF0:
Ok, I thought about the 74hc86. |
| TurboTom:
I did some analyzing of this GPSDO and indeed, both versions work identically. They are both a hardware PLL with one of the XOR gates of the HC86 as phase comparator. The GPS module outputs a 1kHz square wave based on the GPS satellite atomic clocks. The OVCXO (ovenized voltage controlled crystal oscillator) 10MHz output signal is divided by 1000 10'000 (thanks to @Hans_18T for making me aware of my mistake... |O) -- by the ATMEGA328 on the older versions of the GPSDO and by the two HC390 double decade counters on the newer. The HC390 route is straight forward (except that by setting the jumpers R25, 26 or 30, different divisors can be selected, maybe to adapt to possible different GPS module choices), while in case of the ATMEGA's internal division, things are a little more tricky. Since the microcontroller's counter/timers always synchronize the clock input to their own clock frequency, using one of these channels to scale the OVCXO frequency would be a bad idea. Instead, some of the OVCXO's (buffered) output signal is fed via C6 to the PB6/OSC1 terminal of the ATMEGA in order to synchronize the attached ceramic resonator to the OVCXO while still permitting the microcontroller to run if the external oscillator signal isn't present. One of the ATMEGA's PWM/Waveform generator modules is used to exactly divide the clock frequency by 1000 10'000. I'm not sure what may be the advantage of the external dividers that are getting used in the later GPSDOs, but I'm pretty certain that the differences are marginal, since the frequency generation inside the ATMEGA's PWM module is performed completely in hardware and not desturbed by CPU operation. Other than dividing the OVCXO frequency, the ATMEGA only performs supervisory jobs like monitoring the GPS module's serial data stream for a GPS lock and digitizing/checking the phase comparator's output signal for droop (to identify a PLL lock) and driving the signalling LEDs accordingly. The phase comparator signal is filtered through an analog low pass (R59/C77) and then buffered / amplified by U11 before it's fed to the voltage control input of the oscillator. And that's all about this GPSDO. Simple as can be. The big advantage of the new version is that the designer did without the buck converter to generate the 5V supply. It's now all linear, granting much less potential for interference. Maybe this little write-up helps some fellow member to better understand the working principles of this GPSDO and gives some hints to those who are inclined to buying one of these units. Edit: Corrected the divisor specification |
| Noy:
I think i have a similar device but my is named BG7TBL e-GPSDO with PCB from 2020. Pictures in the majn GPSDO thread. The seller says slightly different HW mounted and other firmware and cause of this slightly more accurate than PLL-GPSDO shown here. Is the Atmel talking / configurating the GPS Module? I'm thinking of changing the module to MAX-M8W (already have one here + adapter footprint PCB) or buying a new Neo-M9N to get a faster / more stable fix with concurrent GNSS. Currently its not so stable like i would... :horse: Also thinking about another antenna, but which one is the best for <20€?: Taoglas: https://www.mouser.de/datasheet/2/398/AA.166.301111-1508818.pdf https://www.mouser.de/datasheet/2/398/AA.162.301111-1508634.pdf Or Beitian (search for in Aliexpress): BA55 or BA35 |
| TurboTom:
@Noy - You are right: The ATMEGA initially sends a config sequency to the GPS module (I recorded it but unfortunately had the decoder set to ASCII, and the information may be binary - CSV file attached anyway). If you need it in binary format, I can check it again with the proper decoder settings. But since you've got one of these GPSDOs as well, it won't be a problem for you to record it yourself... ;) Otherwise, the ATMEGA monitors the GPS module's output and continues to send status information to it -- not sure if that gets embedded to the GPS module's output, at least I didn't find any. The status information is: *** MINI GPSDOBG7TBL 20171008 which gets transmitted directly after the initialization sequence, and then, as long as there isn't a complete lock, approx. every five seconds: ALM:GPS NO FIX! ALM:PLL UNLOCK Once the GPS has a fix, it only sends: ALM:PLL UNLOCK After the PLL achieved lock, no status message gets sent anymore. I guess the initialization sequence configures the GPS module to output a 1kHz frequency signal on pin 3 while pin 1 is (somehow -- undocumented feature??) set to provide the 1Hz signal. Since the GPSDO supplies 5V to the GPS antenna output, your first mentioned (and actually slightly better) antenna option is not available (unless you reconfigure the polyfuse inside the GPSDO to the 3.3V position). I found my GPSDO to work well with the supplied active antenna, now even behind the window. It appears to be normal, that after initial PLL lock, it may unlock and re-lock again up to three times before it finally gets stable. The "lock" indicator isn't a hard limit, it only indicates that the remaining phase drift is below a certain margin. Accuracy still gets a little better for a while after a lock is indicated. |
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