Products > Test Equipment
New Rigol DS7000
iMo:
Ok, it uses a dual core ARM CPU w/ 512MB of ram in a Xilinx Zynq FPGA
--- Quote ---Xilinx Zynq Platform, model: Xilinx Zynq
SMP: Total of 2 processors activated.
--- End quote ---
So the new "Asic(s)" is most probably about front-ends/ADCs/sample_buffers/DSP only..
thn788:
--- Quote from: EEVblog on August 08, 2018, 06:01:30 am ---Boot output:
--- Code: ---...
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
...
l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 512 kB
...
Brought up 2 CPUs
SMP: Total of 2 processors activated.
...
Calibrating delay loop... 1731.78 BogoMIPS (lpj=8658944)
...
--- End code ---
--- End quote ---
Apparently a Xilinx Zynq with Dual-Cortex-A9 and 512 KB L2-Cache, which seems to be running at 866 MHz. According to https://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf this might be a Zynq Z-7010, Z-7015, or Z-7020 (assuming Rigol doesn't use over- or underclocked CPUs).
And is this an open, working Linux prompt without password protection?
--- Quote from: EEVblog on August 08, 2018, 06:01:30 am ---Boot output:
--- Code: ---...
rcS Complete
[1B][1;31m<root@rigol>[1B][0mrpcbind: cannot create socket for udp6
...
--- End code ---
--- End quote ---
Andrew:
Date Sheet page 22:
"Note[2]: 1mV/div and 2mV/div are a magnification of 4mV/div setting..."
Where have we seen that before? :)
2N3055:
--- Quote from: Andrew on August 08, 2018, 09:48:28 am ---Date Sheet page 22:
"Note[2]: 1mV/div and 2mV/div are a magnification of 4mV/div setting..."
Where have we seen that before? :)
--- End quote ---
On Keysight DSOX3000T and 4000 series for starters......
Dwaine:
They really need to update their linux kernel, gcc and toolchain. Spectre and meltdown anyone. And the performance improvements they are missing....
Come on Jim.....
Linux version 3.12.0-xilinx (rigolee@Jim) (gcc version 4.8.1 (Sourcery CodeBench Lite 2013.11-53) ) #35 SMP PREEMPT Tue May 22 17:58:17 CST 2018
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