Author Topic: New Rigol DS7000  (Read 56020 times)

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Online jjoonathan

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Re: New Rigol DS7000
« Reply #125 on: July 28, 2018, 12:52:35 pm »
I agree, looking like the UI is responsive throughout the video - only that it is waiting for a trigger event to occur.

I'm looking at the considerable delay between the trace appearing and the FFT updating. It's a good fraction of a second.
 

Offline 2N3055

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Re: New Rigol DS7000
« Reply #126 on: July 28, 2018, 02:40:34 pm »
I agree, looking like the UI is responsive throughout the video - only that it is waiting for a trigger event to occur.

I'm looking at the considerable delay between the trace appearing and the FFT updating. It's a good fraction of a second.

It says 125 Mega samples....  so it's probably not a 32k FFT..
 
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Offline carl0s

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Re: New Rigol DS7000
« Reply #127 on: July 28, 2018, 03:00:39 pm »
I agree, looking like the UI is responsive throughout the video - only that it is waiting for a trigger event to occur.

You can judge here: https://youtu.be/zrfG9wtQjh0?t=98

The big color-graded FM demo was static for a reason  ::)

You mean the slow refresh? But isnt that just because its being triggered externally by the spec an?

And also, that is on a 125 Megasamples... Not  32kS, not 4MS.. So that looks interesting.

It seems a very promising hardware. It will drill down to bugs. If it won't be buggy then a good scope.
As far as U/I goes, that's personal preference..

From what I could see browsing through the manual, it has many good things.

The problems I see:
  • One thing I don't like is that in manual math seems very rudimentary. The way it is described in manual it doesn't have advanced mode, meaning arbitrary math. That means math, as described, is on the level of ds100Z not ds4000. That's not good.
  • Math source can be only channel and ref. No math to math piping. R&S RTM3000 does it right.
  • Because of 2. you cannot perform FFT on math. That would be awesome. Picoscope, R&S RTM3000, Tek MDO3000/4000 and others can do it...
  • On all list/table based U/I elements, use of screen estate is inefficient. Lots of small windows in the middle of the screen,overlapping over other important data, no docking... R&S is doing it right, Lecroy too.  Keysight is kinda OK.
I'm sure if I played with it for some time I would find more things that are suboptimal for a scope that wants to be midrange..

and those god damn button shapes. I can't un-see it now on my DS1054Z. There's no logic to it at all. I think I have been able to fathom out some of the sort of symmetry that has made them choose which corners to chop off which buttons, but it's utterly insane and no other equipment has weird randomly shaped buttons.
--
Carl
 

Offline Fungus

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Re: New Rigol DS7000
« Reply #128 on: July 28, 2018, 03:05:53 pm »
and those god damn button shapes. I can't un-see it now on my DS1054Z. There's no logic to it at all. I think I have been able to fathom out some of the sort of symmetry that has made them choose which corners to chop off which buttons, but it's utterly insane and no other equipment has weird randomly shaped buttons.

You won't even see them after it's been on your bench for two days.

 

Offline 2N3055

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Re: New Rigol DS7000
« Reply #129 on: July 28, 2018, 03:24:13 pm »
and those god damn button shapes. I can't un-see it now on my DS1054Z. There's no logic to it at all. I think I have been able to fathom out some of the sort of symmetry that has made them choose which corners to chop off which buttons, but it's utterly insane and no other equipment has weird randomly shaped buttons.

Yeah, while i kinda agree with you it is not some fancy design, i couldn't care less. It's a tool...
I personally think design (apart from ergonomics) is being given too much attention ( ^-^ ).. I abhor form over function...
I DO care about clear logical layout, that support hierarchy of instruments menus and functions...
 

Offline snoopy

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Re: New Rigol DS7000
« Reply #130 on: July 30, 2018, 08:30:06 am »
This scope has performance in spades. The established brands should be worried. I recall that it was going to be released at last years Electronex show in Melb but was held back. Looks like they spent a year ironing out the bugs before they were going to make it public. From the videos and comparison to the TEK MDO3000 it looks quite impressive.

cheers
 

Offline hendorog

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Re: New Rigol DS7000
« Reply #131 on: July 30, 2018, 08:43:55 am »
I agree, looking like the UI is responsive throughout the video - only that it is waiting for a trigger event to occur.

I'm looking at the considerable delay between the trace appearing and the FFT updating. It's a good fraction of a second.

Hmm, yes there is something going on there.
 

Offline bson

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Re: New Rigol DS7000
« Reply #132 on: July 30, 2018, 08:57:59 am »
With 8bit input you get 8bit output. Any advanced math co-processor or any fastest ASIC cannot change that..
Any band filtering, even decimation using an elementary boxcar filter, will enhance precision.
 

Offline nctnico

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Re: New Rigol DS7000
« Reply #133 on: July 30, 2018, 09:31:34 am »
With 8bit input you get 8bit output. Any advanced math co-processor or any fastest ASIC cannot change that..
Any band filtering, even decimation using an elementary boxcar filter, will enhance precision.
Not at all. You may get more resolution but only if there is enough noise AND the ADCs are linear (which they aren't) otherwise you'll see a fantasy signal.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 
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Offline Hydrawerk

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Re: New Rigol DS7000
« Reply #134 on: August 04, 2018, 06:40:04 pm »
I am looking formward to the review. https://twitter.com/eevblog/status/1024170698275618817
It is already online.
« Last Edit: August 05, 2018, 09:09:30 pm by Hydrawerk »
Amazing machines. https://www.youtube.com/user/denha (It is not me...)
 
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Offline imo

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Re: New Rigol DS7000
« Reply #135 on: August 05, 2018, 12:23:27 pm »
With 8bit input you get 8bit output. Any advanced math co-processor or any fastest ASIC cannot change that..
Any band filtering, even decimation using an elementary boxcar filter, will enhance precision.
Not at all. You may get more resolution but only if there is enough noise AND the ADCs are linear (which they aren't) otherwise you'll see a fantasy signal.
There are some basic laws of physics which, as of today and in this Universe, still apply. You get samples with 8bits of amplitude "V", and, you get them the time "T" apart. Creating any other better values out of these 2 is just the "fantasy", correct.
« Last Edit: August 05, 2018, 12:37:25 pm by imo »
 

Offline 2N3055

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Re: New Rigol DS7000
« Reply #136 on: August 05, 2018, 03:02:56 pm »
With 8bit input you get 8bit output. Any advanced math co-processor or any fastest ASIC cannot change that..
Any band filtering, even decimation using an elementary boxcar filter, will enhance precision.
Not at all. You may get more resolution but only if there is enough noise AND the ADCs are linear (which they aren't) otherwise you'll see a fantasy signal.
There are some basic laws of physics which, as of today and in this Universe, still apply. You get samples with 8bits of amplitude "V", and, you get them the time "T" apart. Creating any other better values out of these 2 is just the "fantasy", correct.

E... No.

(don't attack me for lack of mathematical rigor here... it is deliberate)

If you do have A/D converter that is 8 bits for example, and very linear and monotonic (it has accurate step).  And you have signal that is right between two steps, what you get on the output?
Signal will have a certain amount of noise in it, and if it is random noise, you will get random rounding to lower and upper value on output of A/D converter. In a 100 samples, average of those 100 samples would be pretty much exactly in between bits. If signal was a little lower, you would get more flicking to low value and less on high value.
In a way it would look like a PWM modulation between two bits, and average of several measurements would converge to a true value, to an accuracy higher that A/D has.

Sometimes noise is deliberately introduced, that's called dithering.

It is valid technique, but has limitations. 

EDIT: Sorry I pressed something and it got posted before I was finished.
« Last Edit: August 05, 2018, 03:12:30 pm by 2N3055 »
 

Offline nctnico

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Re: New Rigol DS7000
« Reply #137 on: August 05, 2018, 03:11:16 pm »
With 8bit input you get 8bit output. Any advanced math co-processor or any fastest ASIC cannot change that..
Any band filtering, even decimation using an elementary boxcar filter, will enhance precision.
Not at all. You may get more resolution but only if there is enough noise AND the ADCs are linear (which they aren't) otherwise you'll see a fantasy signal.
There are some basic laws of physics which, as of today and in this Universe, still apply. You get samples with 8bits of amplitude "V", and, you get them the time "T" apart. Creating any other better values out of these 2 is just the "fantasy", correct.

E... NO.

(don't attack me for lack of mathematical rigor here... it is deliberate)

If you do have A/D converter that is 8 bits for example, and very linear and monotonic (it has accurate step).  And you have signal that is right between two steps, what you get on the output?
Signal will have a certain amount of noise in it, and if it is random noise, you will get random rounding to lower and upper value on output of A/D converter. In a 100 samples, average of those 100 samples would be pretty much exactly in between bits. If signal was a little lower, you would get more flicking to low value and less on high value.
In a way it would look like a PWM modulation between two bits, and average of several measurements would converge to a true value, to an accuracy higher that A/D
First of all the noise will need to have a higher amplitude than 1 LSB, secondly that noise would need to have a perfect Gaussian distribution. In reality 8 bit ADCs are made to have 8 bits. Any extra linearity is just a waste of money & effort because that is not the goal (IF it is even possible to get the extra linearity).
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline pascal_sweden

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Re: New Rigol DS7000
« Reply #138 on: August 06, 2018, 10:48:24 am »
It could have been a nice order configuration option from Rigol that the user can select a Matte display or Glossy display upon ordering the oscilloscope.

Some people prefer Glossy, while other people hate it. In fact I personally prefer Matte display so much better, as the reflections on a Glossy display can make the oscilloscope display useless in some lab environments.

Or if it is too hard to implement a configuration option, why not just stick with a Matte display which works for most people?

What do other people on this forum think about this? Why would one like to have a Glossy display in the first place? Is there any advantage at all, or is it really only a disadvantage as such?
« Last Edit: August 06, 2018, 10:51:17 am by pascal_sweden »
 

Offline 2N3055

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Re: New Rigol DS7000
« Reply #139 on: August 06, 2018, 11:00:21 am »
Glossy screens are crap. There is no option where they are better that matte... Glossy is cheap multimedia crap that is so ubiquitous because tablets use them.  Which would be so much better with matte screens too.  And matte screens show less smudges from fingerprints ...
I guess  it needs additional cost to make matte screen and apply anti reflective coating.
 

Offline pascal_sweden

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Offline 2N3055

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Re: New Rigol DS7000
« Reply #141 on: August 06, 2018, 12:08:13 pm »
Absolutely they could... And they should come already laminated on screen from factory....
 

Offline pascal_sweden

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Re: New Rigol DS7000
« Reply #142 on: August 06, 2018, 12:27:57 pm »
Anybody in touch here with senior management from Rigol? Please make them talk to 3M management for a good bulk rate on factory mounted anti-glare filters! :)
 

Offline bugi

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Re: New Rigol DS7000
« Reply #143 on: August 06, 2018, 02:15:16 pm »
Glossy screens are crap. There is no option where they are better that matte... Glossy is cheap multimedia crap that is so ubiquitous because tablets use them.  Which would be so much better with matte screens too.  And matte screens show less smudges from fingerprints ...
I guess  it needs additional cost to make matte screen and apply anti reflective coating.
Uh, my experience so far has been such that matte screens are a nightmare to clean from fingerprints (or any smudges) and the fingerprints show up just as well as on glossy (until you try to wipe them off; glossy gets clean in single wipe, matte just gets worse and needs microfiber and soap water and still needs half a minute of gentle wiping). All the way to the point of getting permanent marks on my anti-reflection coating of one of my displays, because it seems impossible to get whatever crap ended up in the microscopic pits... Also, most matte surfaces are, afaik, based on some form of plastic/non-hard material, which means that if you use it as a touchscreen, it will not be nice even matte for long (e.g. the most used spots on a matte-surfaced keyboards get glossy in less than couple years, and the spots that get hit by fingernails much faster).

There must be a reason why majority of touchscreens are glossy, even on the most expensive high end devices, which could (and would) use more expensive choices. Best examples are some expensive laptop models which offered both touch and non-touch display versions; the touch ones were always glossy, non-touch ones had always anti-reflection.

For non-touch displays I always choose some anti-reflection stuff, but touch ones... until they can figure out a type that can last years without getting wear marks and a method to clean them properly, glossy it is for me.
 

Offline nctnico

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Re: New Rigol DS7000
« Reply #144 on: August 06, 2018, 02:45:02 pm »
I have two touch screen scopes with glossy screens and it really is not an issue at all.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 
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Offline carl0s

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Re: New Rigol DS7000
« Reply #145 on: August 06, 2018, 07:45:53 pm »
I am looking formward to the review. https://twitter.com/eevblog/status/1024170698275618817
It is already online.


Yes you're right Dave, that physical interface is a complete.. a complete failure.

My DS1054Z is bad, but that has twice as much of everything. It extends into the square corners and face of the housing itself.

FFS Rigol, soften the edges of everything. Make buttons square with slightly radiused corners, or just round, maybe with a convex front, orient all the text horizontally, and don't mix conflicting of fonts.
If a button says "Back" on it, give it an arrow pointing to the left (back), not an arrow pointing up.

I know it's not of primary importance, but it's pretty important. It's like decent spelling and grammar in business.
--
Carl
 

Offline Wolfgang

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Re: New Rigol DS7000
« Reply #146 on: August 06, 2018, 09:11:28 pm »
Not true. With 8Bits resolution on paper, you will get quite less bits in reality, due to noise, nonlinearity and other issues.
The ENOB value should be compared. The RIGOL does not even have this specified (prove me wrong). I guess that its about 6-7Bits across full bandwidth, not more.
 

Offline Wolfgang

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Re: New Rigol DS7000
« Reply #147 on: August 07, 2018, 09:23:51 pm »
I cant help the impression that the discussion here focusses a bit much on aspects of aesthetics and product exterior design and not so much on the features and specs of the unit. The same thing happened with other equipment like the RIGOL electronic load, e.g.  There were serious flaws, but the majority of the review minutes spent was on design aspects if button should be labeled left to right or if backwards slanted characters should be allowed by law. This, IMHO, is the wrong priority for a technical forum (dont get me wrong - I dont like their design too much myself - but I dont think it is the most important thing to talk about in such overwhelming detail).

So, I suggest to focus on features, compliance to specs, bugs, usability, reliability, ... first, and then all the aesthetic aspects. If handled the other way such a thread gets filled with gossip because everyone has a different taste.  :)


 
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Offline 1anX

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Re: New Rigol DS7000
« Reply #148 on: August 07, 2018, 09:35:24 pm »
So, I suggest to focus on features, compliance to specs, bugs, usability, reliability, ... first, and then all the aesthetic aspects. If handled the other way such a thread gets filled with gossip because everyone has a different taste.  :)
I agree with your observation! The thing is though, all we have so far is Dave's first impression of the scope. He is about to perform the teardown and then the review later. So really this being the first 3rd party review on the internet we are all waiting on the details of this scope to be revealed.

The real strengths and weaknesses are yet to to be revealed and I for one am curious if Rigol have made a step up with this new scope.
 

Offline EEVblog

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Re: New Rigol DS7000
« Reply #149 on: August 08, 2018, 06:01:30 am »
Boot output:

Code: [Select]


U-Boot 2014.01.Rigolee.dirty (2018.03.27 - 15:01:25)

I2C:   ready
Memory: ECC disabled
DRAM:  448 MiB
DPU:   20170604
NAND:  OnDie ECC supported, 1024 MiB
zynq-In:    serial
zynq-Out:   serial
zynq-Err:   serial
Net:   Gem.e000b000
BootParam=0x0
Hit any key to stop autoboot:  0

NAND read: device 0 offset 0xd900000, size 0x3591fd
รพ
NAND read: device 0 offset 0xd900000, size 0x8
 8 bytes read: OK

NAND read: device 0 offset 0xd500000, size 0x12c008
 1228808 bytes read: OK
Loading logo, x=310,y=247,width=404,height=89

NAND read: device 0 offset 0xe100000, size 0xd8d690
 14210704 bytes read: OK
## Loading kernel from FIT Image at 03000000 ...
   Using 'rootfs@1' configuration
   Trying 'kernel@1' kernel subimage
     Description:  Flamingo Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x030000f8
     Data Size:    3296960 Bytes = 3.1 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00100000
     Entry Point:  0x00100000
     Hash algo:    sha1
     Hash value:   3baba24f03cf5590e2c536eaa322b6dba603dabf
   Verifying Hash Integrity ... sha1+ OK
## Loading ramdisk from FIT Image at 03000000 ...
   Using 'rootfs@1' configuration
   Trying 'ramdisk@1' ramdisk subimage
     Description:  Flamingo-Update-Ramdisk
     Type:         RAMDisk Image
     Compression:  gzip compressed
     Data Start:   0x033276fc
     Data Size:    10901113 Bytes = 10.4 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha1
     Hash value:   55bdcbebccba845da403130143793ee0135e53a1
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 03000000 ...
   Using 'rootfs@1' configuration
   Trying 'fdt@1' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x033250ac
     Data Size:    9613 Bytes = 9.4 KiB
     Architecture: ARM
     Hash algo:    sha1
     Hash value:   4b3f2131fa7fc01da8110e0b15068def40b971c5
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x33250ac
   Loading Kernel Image ... OK
   Loading Ramdisk to 1b099000, end 1bafe679 ... OK
   Loading Device Tree to 1b093000, end 1b09858c ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 3.12.0-xilinx (rigolee[member=167213]Jim[/member]) (gcc version 4.8.1 (Sourcery CodeBench Lite 2013.11-53) ) #35 SMP PREEMPT Tue May 22 17:58:17 CST 2018
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Xilinx Zynq Platform, model: Xilinx Zynq
Memory policy: Data cache writealloc
PERCPU: Embedded 8 pages/cpu @c09ef000 s8384 r8192 d16192 u32768
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 113792
Kernel command line: console=ttyPS0,115200 no_console_suspend, root=/dev/ram rw
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 437424K/458752K available (4185K kernel code, 255K rwdata, 1716K rodata, 176K init, 178K bss, 21328K reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xdc800000 - 0xff000000   ( 552 MB)
    lowmem  : 0xc0000000 - 0xdc000000   ( 448 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc05cb76c   (5902 kB)
      .init : 0xc05cc000 - 0xc05f80c0   ( 177 kB)
      .data : 0xc05fa000 - 0xc0639d78   ( 256 kB)
       .bss : 0xc0639d84 - 0xc0666924   ( 179 kB)
Preemptible hierarchical RCU implementation.
Dump stacks of tasks blocking RCU-preempt GP.
RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
NR_IRQS:16 nr_irqs:16 16
ps7-slcr mapped to dc802000
Zynq clock init
sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms
Console: colour dummy device 80x30
Calibrating delay loop... 1731.78 BogoMIPS (lpj=8658944)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0xc03f7df0 - 0xc03f7e48
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 512 kB
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated.
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
regulator-dummy: no parameters
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
gpio->base_addr is:0xdc84e000
The gpio irq num is:52
zynq_gpio e000a000.ps7-gpio: gpio at 0xe000a000 mapped to 0xdc84e000
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq_ocm f800c000.ps7-ocmc: ZYNQ OCM pool: 256 KiB @ 0xdc880000
bio: create slab <bio-0> at 0
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti[member=183778]linux[/member].it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP: reno registered
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 10644K (db099000 - dbafe000)
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
NTFS driver 2.1.30 [Flags: R/W].
msgmni has been set to 875
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
DPU:Map vRam to 0xdca00000
DPU:Map iReg to 0xdcc00000
DPU:Ver=0x20170604
dma-pl330 f8003000.ps7-dma: unable to set the seg size
dma-pl330 f8003000.ps7-dma: Loaded driver for PL330 DMAC-2364208
dma-pl330 f8003000.ps7-dma: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 59, base_baud = 6249999) is a xuartps
console [ttyPS0] enabled
xuartps e0001000.serial: failed to get alias id, errno -19
e0001000.serial: ttyPS1 at MMIO 0xe0001000 (irq = 82, base_baud = 6249999) is a xuartps
brd: module loaded
loop: module loaded
xspips e0006000.ps7-spi: master is unqueued, this is deprecated
xspips e0006000.ps7-spi: at 0xE0006000 mapped to 0xDC858000, irq=58
libphy: XEMACPS mii bus: probed
xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
ULPI transceiver vendor/product ID 0x0424/0x0009
ULPI integrity check: passed.
ULPI transceiver vendor/product ID 0x0424/0x0009
ULPI integrity check: passed.
xusbps-ehci xusbps-ehci.1: Xilinx PS USB EHCI Host Controller
xusbps-ehci xusbps-ehci.1: new USB bus registered, assigned bus number 1
xusbps-ehci xusbps-ehci.1: irq 76, io mem 0x00000000
xusbps-ehci xusbps-ehci.1: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
rtc-rx8010sj 0-0032: Update timer was detected
rtc-rx8010sj 0-0032: rtc core: registered rtc-rx8010sj as rtc0
xi2cps e0004000.ps7-i2c: 100 kHz mmio e0004000 irq 57
zynq-edac f8006000.ps7-ddrc: ecc not enabled
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xd3 (Micron MT29F8G08ADADAH4), 1024MiB, page size: 2048, OOB size: 64
Bad block table found at page 524224, version 0x01
Bad block table found at page 524160, version 0x01
13 ofpart partitions found on MTD device pl353-nand
Creating 13 MTD partitions on "pl353-nand":
0x000000000000-0x000000040000 : "Env"
0x000000100000-0x000004100000 : "DATA"
0x000004100000-0x000004500000 : "Bmp"
0x000004500000-0x000004900000 : "Bmp1"
0x000004900000-0x000005100000 : "Bit1"
0x000005100000-0x000007100000 : "Sys1"
0x000007100000-0x00000d500000 : "App1"
0x00000d500000-0x00000d900000 : "Bmp2"
0x00000d900000-0x00000e100000 : "Bit2"
0x00000e100000-0x000010100000 : "Sys2"
0x000010100000-0x000016500000 : "App2"
0x000016500000-0x00001a800000 : "Reserved"
0x00001a800000-0x000040000000 : "User"
TCP: cubic registered
NET: Registered protocol family 17
Registering SWP/SWPB emulation handler
+-----------------------------------------+
|           Touch driver                |
+-----------------------------------------+
usb 1-1: new high-speed USB device number 2 using xusbps-ehci
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 4 ports detected
Touchscreen ProductID: 0x2543
Touchscreen VersionID: 0x0102
input: ssd2543 as /devices/amba.1/e0004000.ps7-i2c/i2c-0/0-0048/input/input0
rtc-rx8010sj 0-0032: setting system clock to 2018-08-08 13:49:57 UTC (1533736197)
RAMDISK: gzip image found at block 0
VFS: Mounted root (ext2 filesystem) on device 1:0.
devtmpfs: mounted
Freeing unused kernel memory: 176K (c05cc000 - c05f8000)
Starting rcS...
++ Mounting filesystem
++ Setting up mdev
++ Starting ftp daemon
rcS Complete
[1B][1;31m<root@rigol>[1B][0mrpcbind: cannot create socket for udp6

rpcbind: cannot create socket for tcp6

2018-08-08 13:50:10: (log.c.166) server started
7 2048 16 2 "/dev/fb0"
 
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