Products > Test Equipment
New Rigol HDO1000 12-bit DSO - BUGs
the Chris:
--- Quote from: thm_w on December 18, 2023, 11:58:31 pm ---Did you report to Rigol?
--- End quote ---
No, but it probably doesn't harm trying. Is there an official way to report bugs?
thm_w:
--- Quote from: the Chris on December 21, 2023, 03:35:01 pm ---
--- Quote from: thm_w on December 18, 2023, 11:58:31 pm ---Did you report to Rigol?
--- End quote ---
No, but it probably doesn't harm trying. Is there an official way to report bugs?
--- End quote ---
You can send an email to info-europe@rigol.com in EU or help@rigol.com for NA. They will respond back with a confirmation and add to list of bugs.
edit: I was actually on 2.11 and most of the 0.000V Dev issues seem to be fixed on 2.12, but not all. For Frequency I had it get stuck on a certain Dev value and never change. Which has to be wrong if its calculated based on the last 1,000 points. I assuming its storing those numbers, as the max you can set is 100,000.
thunderbolt93:
I tried that with FW 2.12 and noticed something
there seems to be some jitter of about 2ns when using the external trigger input.
Both screenshots are taken with infinite persistance
TurboTom:
It's not a bug, it's a feature ;). See pg. 10 of Rigol's HDO1000 Data Sheet document. There you'll find jitter for the external trigger input to be specified at < 1ns rms (which equals <2ns pp or even more, depending on the histogram), exactly what one would expect from an all-digital trigger system that had been "extended" with an additional one-bit ADC (comparator...) for the fifth, external trigger input. Obviously, for this input, an interpolative trigger, based on the waveform isn't possible, hence the jitter of an interval that is defined by the speed the sampling engine's FPGA can process the trigger comparator input signal.
What's much more worrying is the trigger jitter that is present at AC and HF trigger coupling as had been reported by others before. That shouldn't be there and Rigol will have to take care of this.
gf:
--- Quote from: TurboTom on December 25, 2023, 12:07:27 pm ---It's not a bug, it's a feature ;). See pg. 10 of Rigol's HDO1000 Data Sheet document. There you'll find jitter for the external trigger input to be specified at < 1ns rms (which equals <2.8ns pp), exactly what one would expect from an all-digital trigger system that had been "extended" with an additional one-bit ADC (comparator...) for the fifth, external trigger input. Obviously, for this input, an interpolative trigger, based on the waveform isn't possible, hence the jitter of an interval that is defined by the speed the sampling engine's FPGA can process the trigger comparator input signal.
--- End quote ---
In principle, it would have been possible to measure the time interval between the trigger point (as determined by the comparator) and the ADC clock edge with a TDC, but it was obviously a cost-saving design decision not to do it.
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