Tektronix 2465 MAME emulation

[siggi]

I think the chip is generating it itself.  It has the 5MHz clock input, so it has a source.  It's also responsible for the CAL output, so arbitrary clock generation in this chip already exists in at least one place.

Yeah, the holdoff function is also highly programmable. The input register has five bits for trigger holdoff, plus it's adjustable with the DAC. Maybe this is just a really fast autosweep - though I'm surprised to see what I've termed A-triggered bit set for those sweeps. There is a "FREE RUN" bit in the trigger dies, so maybe that's used here - I'll play with the emulator a bit, see if I can figure out what the various modes are.

Is this important?  I can capture all the pins above at once with the scope or the Saleae if you need to know what threy're doing, but maybe I should focus on the other bits in TSO?

I'm not sure that this is important, though I suspect it might be necessary to understand this in due course for the emulator to pass the 05 tests. I'm more interested to know about the bits in the TSO, particularly if there are e.g. "[AB] sweep in progress" and "[AB] triggered" bits.

[siggi]

Is this important?  I can capture all the pins above at once with the scope or the Saleae if you need to know what threy're doing, but maybe I should focus on the other bits in TSO?

So the "Theory of Operation" section of the service manual has this to say:

Trigger and Sweep Activity (Status)
The activity of the Trigger and Sweep circuits, as indicated by the /SGA, /SGB, /TSA, and /TSB lines, is reported to the Microprocessor via the TSO (trigger status output) line when clocked by the TSS (trigger status strobe) signal.

So /TSA and /TSB are inputs to the Display Sequencer, and not outputs from it, as I had surmised. Presumably these four account for 4 bits of the TSS, with the a fifth bit being the "not single sequence underways".

I'm not sure that this is important, though I suspect it might be necessary to understand this in due course for the emulator to pass the 05 tests.

Mkay, I think this is simply a really fast auto sweep. I'm still trying to figure out how auto sweep works, though by diffing the register settings for the same sweep in AUTO vs NORM I see this:

Code: [Select]

diff  AUTO.txt NORM.txt
35,37c35,37
< :trig_a: 0xFA
<   -TM0-1, Not Trigger Mode: 1(FAST_COMPARE)
<   -FR, Not Free Run, Continuous Trigger Gate: 0
---
> :trig_a: 0xFF
>   -TM0-1, Not Trigger Mode: 3(SWEEP)
>   -FR, Not Free Run, Continuous Trigger Gate: 1
44,45d43
So in other words, AUTO is FAST_COMPARE mode with the continuous trigger gate, whereas NORM is SWEEP mode with no continuous trigger gate.
I guess in FAST_COMPARE, the sweep triggers on the first of /TGA|/TRIG or THO - or maybe the sweep triggers on the falling edge of THO on auto sweep?

[MarkL]

Ok, this took a bit (pun intended?) of playing to come up with a model of what's happening in TSO.  At the moment it fits my current set of observations, but you'll probably find something that's inconsistent.

Sorry I'm not including data dumps and screen shots; there were just too many combinations to document it all.  If there's a particular operating condition(s) you'd like to see, please let me know and I will grab a screen and data capture.


Current guess at lower TSO bits 3/9/2023
----------------------------------------

"now" refers to the interval when TSO is being read out (polled).

TSO8..TSO1
----------
0xxx xxxx   /SGB remained high since last poll
1xxx xxxx   /SGB transitioned low after last poll, or is low now

x01x xxxx   /SGA pin is low now
x11x xxxx   /SGA pin toggled since last poll
x10x xxxx   /SGA pin is high now

xxx0 1xxx   /TSB pin is low now
xxx1 1xxx   /TSB pin toggled since last poll
xxx1 0xxx   /TSB pin is high now

xxxx x01x   /TSA pin is low now
xxxx x11x   /TSA pin toggled since last poll
xxxx x10x   /TSA pin is high now

xxxx xxx0   SNGL mode not READY (sweep done)
xxxx xxx1   All other trigger modes

Other notes:

- /TSB continues to indicate B trigger status, whether B trigger is in
  use or not.

- /TSA is continuously high or low when free-running in AUTO mode
  (*not* AUTO LVL mode), depending on if A trigger voltage level is
  completely above or below the input signal.

[siggi]

Current guess at lower TSO bits 3/9/2023
----------------------------------------

"now" refers to the interval when TSO is being read out (polled).

TSO8..TSO1
----------
0xxx xxxx   /SGB remained high since last poll
1xxx xxxx   /SGB transitioned low after last poll, or is low now

x01x xxxx   /SGA pin is low now
x11x xxxx   /SGA pin toggled since last poll
x10x xxxx   /SGA pin is high now

xxx0 1xxx   /TSB pin is low now
xxx1 1xxx   /TSB pin toggled since last poll
xxx1 0xxx   /TSB pin is high now

xxxx x01x   /TSA pin is low now
xxxx x11x   /TSA pin toggled since last poll
xxxx x10x   /TSA pin is high now

xxxx xxx0   SNGL mode not READY (sweep done)
xxxx xxx1   All other trigger modes

Wow, this is awesome. Just to make sure I understand correctly: the x11x (toggled) state is latching - e.g. if the pin in question has toggled, it's going to stay in the x11x state?

[MarkL]

...
Wow, this is awesome. Just to make sure I understand correctly: the x11x (toggled) state is latching - e.g. if the pin in question has toggled, it's going to stay in the x11x state?

Cool - glad it's useful!

The x11x pattern is latched for one poll cycle, then on the next poll it shows the "now" pin state again.  The x11x state I think is to let the processor know a transition happened  between polls on /SGA. /TSA, or /TSB.

If not clear I can set up an example and post the capture.

[siggi]

While you have the subject on the slab, I'm wondering what is the condition that fires an auto sweep. From looking at the signals between the display sequencer, the trigger hybrid and the sweep hybrids, I'm thinking that it has to be THO transitioning low. This would mean the display sequencer has direct control over the frequency of auto sweep, which almost certainly is related to the reciprocal of sweep speed to maintain something like a steady auto trace brightness across sweep speeds.

Seeing how THO goes to both the trigger and the A-sweep hybrid, my bet is that THO transitioning low to the sweep hybrid is what triggers the auto sweep. Looking at the sweep hybrid schematics, it looks plausible that a low THO would initiate a sweep?
I guess to validate this, you'd need to look at THO in auto sweep vs the trigger hybrid output?

[siggi]

The x11x pattern is latched for one poll cycle, then on the next poll it shows the "now" pin state again.  The x11x state I think is to let the processor know a transition happened  between polls on /SGA. /TSA, or /TSB.

Ah, I get it now. Either state of each line (except B sweep) is represented as a latched bit in the trigger status reg. So a set bit means that a particular state occurred and was latched for a particular signal. So a x11x pair means both states occurred from last read.

I was wondering why the B-sweep doesn't get the same treatment, but then I realized it shouldn't need to, as the B sweep should always be bracketed by the A sweep.

[MarkL]

...
Seeing how THO goes to both the trigger and the A-sweep hybrid, my bet is that THO transitioning low to the sweep hybrid is what triggers the auto sweep. Looking at the sweep hybrid schematics, it looks plausible that a low THO would initiate a sweep?
I guess to validate this, you'd need to look at THO in auto sweep vs the trigger hybrid output?

I'm seeing that the U500 trigger hybrid output, /TGA (pin 18), is static low when the scope is auto sweeping.

/SGA going low indicates the beginning of the sweep, and comparing that to THO it's difficult to say who's first due to the vastly different edge speeds of 18ns vs. 74ns (see below).

THO does start to drop first, so it's conceivable the sweep hybrid is switching on an unusually high (non-TTL) voltage threshold.

EDIT: Let me clarify and say that THO falling is obviously not a result of /SGA falling, but it is not a foregone conclusion that THO falling is causing /SGA to fall.  Only that the timing does support the latter as a possibility.

[siggi]

/SGA going low indicates the beginning of the sweep, and comparing that to THO it's difficult to say who's first due to the vastly different edge speeds of 18ns vs. 74ns (see below).

THO does start to drop first, so it's conceivable the sweep hybrid is switching on an unusually high (non-TTL) voltage threshold.

Yeah, I guess the falling edge of THO is not very time critical, but presumably the rising edge has to be crisp for the trigger and sweep hybrids to be sequenced correctly for a sweep.

I think this confirms that the display sequencer initiates auto sweep through THO, at least the data doesn't contradict that hypothesis .

Now, looking at the tek_made catalog info sheet again, I found this:

Ramp Initiation Sweep Gate Circuitry
Ramp is Initiated by the coincidence of a “LO” at the “Not Trigger”, “Not Auxiliary Trigger" and “Trigger Holdoff” inputs.

which seems to further confirm that the falling edge of THO will initiate a sweep if the trigger strobe didn't beat it to it.

[siggi]

The other feature is "TRIGGER SLOPE SELECTION", where it seems it would be possible to select different trigger slopes for each delay sweep. I don't think the scope offers the possibility of selecting trigger slope per delay sweep - though I may be wrong about that.

So it turns out that in the presence of the CTT option, the 2465 does offer the possibility of triggering on alternate slopes for dual B delay sweeps.
Likewise, in the presence of the CTT option, my 2467 allows setting distinct slopes AND trigger levels for each of the delay sweeps. This allows e.g. automated measurement of pulse width, or - possibly - say automated rise time measurement. The latter would be fairly touchy, though my 2467 does display the trigger level voltage as I'm adjusting it.

As an aside, I find myself pondering how the CTT option does delta delay measurements, for triggered B sweeps in particular. Since the delay sweeps alternate, there's no way to directly measure the time from one B trigger to the other that I can think of. I guess the CTT option has to measure the A to B trigger delay for each delay/trigger/slope setting and then compute the difference?