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| Older logic analyzer question. |
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| gslick:
--- Quote from: TK on May 11, 2017, 11:27:16 pm ---Do you have the schematics for 10300B Z80 preprocessor? I am interested in knowing how to translate the control signals from Z80 to the 4-bit STAT bus that the Z80 inverse assembler needs. --- End quote --- The 10300B STAT signals in least significant order are: /WR - CPU pin 22 /IORQ - CPU pin 20 /RFSH - CPU pin 28 /M1 - CPU pin 27 /WR is fed three times through a 74LS240 inverting buffer/driver for a STAT signal. /IORQ is fed once through a 74LS240 inverting buffer/driver for clock signal, and twice for a STAT signal. /RFSH is fed once through a 74LS241 non-inverting buffer/driver for a clock and STAT signal. /M1 is fed once through a 74LS241 non-inverting buffer/driver for a STAT signal. Maybe the multiple passes for /WR and /IORQ are to delay those signals by a few ns. That is from the Model 64683A Interface Module Z80 Service Information manual part number 64683-90903. I only have a photocopy of the manual. I'll see if I can get it scanned when I have time. |
| TK:
--- Quote from: gslick on May 12, 2017, 02:34:39 am --- --- Quote from: TK on May 11, 2017, 11:27:16 pm ---Do you have the schematics for 10300B Z80 preprocessor? I am interested in knowing how to translate the control signals from Z80 to the 4-bit STAT bus that the Z80 inverse assembler needs. --- End quote --- The 10300B STAT signals in least significant order are: /WR - CPU pin 22 /IORQ - CPU pin 20 /RFSH - CPU pin 28 /M1 - CPU pin 27 /WR is fed three times through a 74LS240 inverting buffer/driver for a STAT signal. /IORQ is fed once through a 74LS240 inverting buffer/driver for clock single, and twice for a STAT signal. /RFSH is once through a 74LS241 non-inverting buffer/driver for a clock and STAT signal. /M1 is fed once through a 74LS241 non-inverting buffer/driver for a STAT signal. Maybe the multiple passes for /WR and /IORQ are to delay those signals by a few ns. That is from the Model 64683A Interface Module Z80 Service Information manual part number 64683-90903. I only have a photocopy of the manual. I'll see if I can get it scanned when I have time. --- End quote --- Thank you gslick. This is the information I needed!!! |
| TK:
--- Quote from: gslick on May 12, 2017, 02:34:39 am --- --- Quote from: TK on May 11, 2017, 11:27:16 pm ---Do you have the schematics for 10300B Z80 preprocessor? I am interested in knowing how to translate the control signals from Z80 to the 4-bit STAT bus that the Z80 inverse assembler needs. --- End quote --- The 10300B STAT signals in least significant order are: /WR - CPU pin 22 /IORQ - CPU pin 20 /RFSH - CPU pin 28 /M1 - CPU pin 27 /WR is fed three times through a 74LS240 inverting buffer/driver for a STAT signal. /IORQ is fed once through a 74LS240 inverting buffer/driver for clock single, and twice for a STAT signal. /RFSH is once through a 74LS241 non-inverting buffer/driver for a clock and STAT signal. /M1 is fed once through a 74LS241 non-inverting buffer/driver for a STAT signal. Maybe the multiple passes for /WR and /IORQ are to delay those signals by a few ns. That is from the Model 64683A Interface Module Z80 Service Information manual part number 64683-90903. I only have a photocopy of the manual. I'll see if I can get it scanned when I have time. --- End quote --- I was using: /M1 /REFR /IORQ //WR (/WR inverted) and feeding the clock signal directly from the Z80, but noticed that Z80 inverse assembler was asking for 2 clock signals and did not know how to generate them. Will try the new interface. |
| gslick:
--- Quote from: TK on May 12, 2017, 12:28:10 pm ---I was using: /M1 /REFR /IORQ //WR (/WR inverted) and feeding the clock signal directly from the Z80, but noticed that Z80 inverse assembler was asking for 2 clock signals and did not know how to generate them. Will try the new interface. --- End quote --- The 64683A / 10300B clock signals are: /MREQ - CPU pin 19 - fed once through a 74LS240 inverting buffer/driver for clock J /IORQ - CPU pin 20 - fed once through a 74LS240 inverting buffer/driver for clock K /RFSH - CPU pin 28 - fed once through a 74LS241 non-inverting buffer/driver for clock L The default 10300B state configuration is to clock on (falling edge of J OR falling edge of K). To filter out refresh cycles the state configuration could be changed to clock on ((falling edge of J OR falling edge of K) AND L high) |
| TK:
--- Quote from: gslick on May 12, 2017, 09:36:17 pm --- --- Quote from: TK on May 12, 2017, 12:28:10 pm ---I was using: /M1 /REFR /IORQ //WR (/WR inverted) and feeding the clock signal directly from the Z80, but noticed that Z80 inverse assembler was asking for 2 clock signals and did not know how to generate them. Will try the new interface. --- End quote --- The 64683A / 10300B clock signals are: /MREQ - CPU pin 19 - fed once through a 74LS240 inverting buffer/driver for clock J /IORQ - CPU pin 20 - fed once through a 74LS240 inverting buffer/driver for clock K /RFSH - CPU pin 28 - fed once through a 74LS241 non-inverting buffer/driver for clock L The default 10300B state configuration is to clock on (falling edge of J OR falling edge of K). To filter out refresh cycles the state configuration could be changed to clock on ((falling edge of J OR falling edge of K) AND L high) --- End quote --- Impressive... Thanks! |
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