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Older logic analyzer question.
cyberbarter:
Thanks TK That's what I needed. Good link. It will get me started.
Much thanks :)
Cyberbarter
kb5mu:
Followup question on the Model 64683A Interface Module Z80 Service Information manual ... are they also buffering the address and data bus signals? That might matter for timing.
A scan of that manual would be nice to have.
Thanks!
-Paul
gslick:
--- Quote from: kb5mu on July 03, 2019, 05:29:47 am ---Followup question on the Model 64683A Interface Module Z80 Service Information manual ... are they also buffering the address and data bus signals? That might matter for timing.
A scan of that manual would be nice to have.
Thanks!
-Paul
--- End quote ---
All of the Z80 signals are buffered once through a 74LS241, with the exception of /MREQ, /IORQ, and /WR which are buffered one or more times through a 74LS240. The buffer outputs are always enabled.
Once through a 74LS241 Non-inverting Octal Buffer and Line Driver:
PIN 30 A0
PIN 31 A1
PIN 32 A2
PIN 33 A3
PIN 34 A4
PIN 35 A5
PIN 36 A6
PIN 37 A7
PIN 38 A8
PIN 39 A9
PIN 40 A10
PIN 1 A11
PIN 2 A12
PIN 3 A13
PIN 4 A14
PIN 5 A15
PIN 14 D0
PIN 15 D1
PIN 12 D2
PIN 8 D3
PIN 7 D4
PIN 9 D5
PIN 10 D6
PIN 13 D7
PIN 16 /INT STAT BIT 7 (Not used by inverse assembler)
PIN 17 /NMI STAT BIT 5 (Not used by inverse assembler)
PIN 18 /HALT STAT BIT 6 (Not used by inverse assembler)
PIN 23 /BUSACK
PIN 25 /BUSREQ STAT BIT 4 (Not used by inverse assembler)
PIN 27 /M1 STAT BIT 3
PIN 28 /RFSH STAT BIT 2, CLOCK L
Once through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 19 /MREQ CLOCK J
Once through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 20 /IORQ CLOCK K
Twice through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 20 /IORQ STAT BIT 1
Three times through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 22 /WR STAT BIT 0
Four 74LS241 total, one 74LS240 total.
gotcha:
Hi gslick
I'd be very interested by a schematics (I read this thread but I have a difficulty to transform the text into something that I could build).
Did you by chance scan the manual ?
Thanks !
gslick:
--- Quote from: gotcha on May 20, 2023, 07:50:14 pm ---Hi gslick
I'd be very interested by a schematics (I read this thread but I have a difficulty to transforl the text into something that I could build).
Did you by chance scan the manual ?
Thanks !
--- End quote ---
I have an original copy of this manual, which includes a schematic of the preprocessor interface:
Model 64683A Interface Module Z80
Service Supplement
HP Part Number 64683-90903
I'll have to get my scanner set up again so I can scan it.
The main thing is that all of the Z80 CPU signals are buffered through either 74LS241 Non-inverting Octal Buffer and Line Drivers, or 74LS240 Inverting Octal Buffer and Line Drivers.
The complication for using the original Z80 Inverse Assembler is that the CPU PIN 22 /WR signal is inverted (routed three times through a 74LS240 Inverting Octal Buffer and Line Driver) when used as STAT Bit 0. If the logic analyzer is attached through flying leads instead of the preprocessor and the /WR signal is not inverted, the original Inverse Assembler will not function correctly.
The original Z80 Inverse Assembler could be modified to work when the /WR signal is not inverted when used for STAT Bit 0. If I have never posted details here on how to do that, I'll have to do that when I make some time to do so.
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