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Older logic analyzer question.
gotcha:
FYI, a Z80 preprocessor documentation (64683-90901) and few others have been given here yesterday: https://forum.vcfed.org/index.php?threads/hp-1650-1651-logic-analyzer-disk-images.53427/#post-1317744
They are now stored in bitsavers : http://bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/
It doesn't seem exactly the same as yours since the reference number differs a bit.
gotcha:
@gslick do you know why /WR is routed 3 times through the 74LS240 ? A single time would have been sufficient to invert the signal.
EDIT: apparently, it's to make sure (through a propagation delay) the right value is sampled by the analyzer.
gotcha:
--- Quote from: gslick on May 21, 2023, 12:34:02 am ---The complication for using the original Z80 Inverse Assembler is that the CPU PIN 22 /WR signal is inverted (routed three times through a 74LS240 Inverting Octal Buffer and Line Driver) when used as STAT Bit 0. If the logic analyzer is attached through flying leads instead of the preprocessor and the /WR signal is not inverted, the original Inverse Assembler will not function correctly.
The original Z80 Inverse Assembler could be modified to work when the /WR signal is not inverted when used for STAT Bit 0. If I have never posted details here on how to do that, I'll have to do that when I make some time to do so.
--- End quote ---
I see 3 things with the preprocessor interface that require a particular attention:
* /WR (STAT0) in indeed inverted by the preprocessor interface and this would require changing the IA 'program'.
If you can explain how, it would be great
* The clocks used by the analyzer to sample data are also inverted by the interface (J=MREQ and K=IORQ).
The data sampling must happen at the end of the read/write.
In the Z80 IA config file, the sampling is then done on clocks falling edge and should be changed to be on rising edge.
This change is easy to do in the Analyzer once we have loaded the config file
* /WR (STAT0) has 2 extra delays and /IORQ (STAT1) has 1 extra delays.
I assume that the goal is to sample /WR and /IORQ values just before the triggering sampling clock (the delay is needed because they change almost at the same time as the clocks)
Knowing that one of the clock (/IORQ) is itself as a value in STAT1, the delay looks mandatory to get the right STAT1 value.
Without these delays, we may experience errors/noise in the disassembly
Due to item 3, I have the feeling that we can't really invert assemble safely the Z80 with flying probes.
We may need an interface, even if we don't want all functionalities and the complexity of the original interface.
My target now is to make experiments with a single 74LS240 just to invert /WR and delay a bit /WR and /IORQ signals for the STAT sampling.
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