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Older logic analyzer question.
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Dan Moos:
I just picked up an HP 1631D logic analyzer on eBay. I don't have it yet, but it was 60 bucks (plus shipping), was advertised as working, and coming from a working environment. It's in many ways inferior to the cheap, 8 channel, Chinese knock-off Saleae clone I have, but it has way more channels, and it tickles my old gear soft spot. Current project is a 6502 single board computer build, and testing it with era appropriate great seems perfect.

In skimming the manual PDF, I see it differentiates between "timing" and "state" channels. Best I can tell is that the state channels require an exterior clock source, whereas the timing channels are asynchronous.

What are the limitations, advantages, purposes, ect, of the two types of channels?

It will come with two "pods" for timing channels, and , 3 for state channels. In the pics, it appears each pod has 8 channels, so any way you cut it, I have a lot more channels than the fake Saleae.
helius:
Timing and State are the two basic LA acquisition modes. They were developed for the parallel bus paradigm, where devices latch data onto an 8-, or 16-, or 32-bit wide bus in response to a clock signal. This was commonly done by bus transceiver chips like the 74LS245 and others. The memory bus directly connected to a microprocessor would be another example.

The names Timing and State should be entirely self-explanatory, since checking the timing, propagation, or delay of signals is a basic engineering problem. Similarly, designing and testing state machines is another basic topic in electronics and computer science.

If you use Timing acquisition to probe such a bus, the analyzer is armed and waiting until its trigger condition is satisfied (the trigger condition can be complex and depend on several events). Then when the condition is true, it begins sampling all of its inputs into memory at a programmed rate, asynchronous to the DUT. This means that with a fast enough acquisition, you can record signal integrity problems such as runt pulses or glitches. Analyzing the data content itself is not feasible in Timing mode (was that two ADDQ #4 instructions, or just one?)

Using State acquisition, the analyzer waits armed until its trigger condition is true, and then records a sample each time the external clock transitions (the clock can be offset by a delay from the time the sample is taken). This is how you snoop the traffic over a bus and decode each word. It also can find defective components, by sampling the inputs and outputs (of an inverter, mux, or shift register) and comparing them. An additional clock qualifier can also be used (for circuits like flip-flops that use both clock and enable signals). State acquisition is not suited to pinpoint signal integrity problems.

More powerful techniques use both State and Timing machines with shared triggers or use one to trigger the other.
ChuckDarwin:
I'll add the when you power up the 1631D you get a menu to individually choose if pods 0 and 1 are in TIMING or join pods 2,3,4 in STATE, and/or use only state or no state at all.  If it is a 31D, you also have a 2 channel 50MHz scope.  The three state pods have a clock lead (J,K or L) to get the clock from an external source.

The unit generates some heat and has a loud fan.  Intake in the back and blows out the right side--keep it to your left in the winter.  You can put a quieter fan in with some caution.

If you want user & service manuals or a getting started sheet, PM.
james_s:
Grab the HP logic analyzer training manual, it will explain how to use timing and state modes. When I got my HP analyzer I used a cheap little FPGA dev board to roughly emulate the original training hardware. It's little more than a counter with an oscillator.
TK:
If you are working with 6502, there is an inverse assembler that works on old HP logic analyzers, in state mode.
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