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Oscilloscope input noise comparison
_Wim_:
--- Quote from: egonotto on December 24, 2018, 12:49:03 am ---I have on my 5243A and 5444B strong spur at 31.25 MHz.
--- End quote ---
Just zoomed in, exactly 31.25Mhz here also
egonotto:
Hello,
31.25MHz * 4 = 125MHz
Perhaps this has to do with the clock frequency of the ADC
Best regards
egonotto
_Wim_:
--- Quote from: egonotto on December 26, 2018, 04:18:31 am ---Hello,
31.25MHz * 4 = 125MHz
Perhaps this has to do with the clock frequency of the ADC
Best regards
egonotto
--- End quote ---
If that is the case, these spurs should move to a different frequency when you run an FFT with 200MHz bandwidth, because I expect the sample rate will then be 400MS/s, which is not dividable by 31.25. Or does is sample at 500MS/s and throws away a bit of the FFT?
Could you post a plot to 200MHz to check this with your 5444B?
Performa01:
--- Quote from: _Wim_ on December 26, 2018, 07:56:42 am ---If that is the case, these spurs should move to a different frequency when you run an FFT with 200MHz bandwidth, because I expect the sample rate will then be 400MS/s, which is not dividable by 31.25. Or does is sample at 500MS/s and throws away a bit of the FFT?
Could you post a plot to 200MHz to check this with your 5444B?
--- End quote ---
PicoTech have pioneered the fully digital trigger system, which requires the ADC to run at full sample rate all the time. This sample data stream is fed into the digital trigger system. Only after that, the sample data get decimated if required to fit shorter record buffer lengths, so we get the effective sample rate at this point.
In other DSOs, where the FFT is not a completely independent operating mode like it is for PicoScopes, one additional decimation step is required whenever the max. FFT length is less than the record length.
Apart from that, the old 3206B samples at 500MSa/s and the FFT shows quite a few strong spurs, starting at 31.25MHz again. That’s probably just the frequency of the clock generator signal, which is then multiplied by a PLL in order to get the required ADC sample clock.
See the noise plot from 1kHz to 200MHz:
Pico 3206B FFT 50Ohm 1kHz-200MHz
EDIT: Please keep in mind that this plot is not directly comparable to the 4000 and 5000 series, because the most sensitive input range is +/-50mV (10mV/div) for the 3206B.
_Wim_:
I sniffed a bit around internally with a DIY near field probe, but could not locate any strong 31.25MHz interference signal. The closest I could find was the 1.5Vdc switchmode regulated which had a spur at 31.20MHz, but also at around 29, 27... that were as strong, and we see only the one at 31.25MHz.
I also enabled all four channels (so only 1 ADC per channel running at 125MS/s, the spur at 31.2MHz remained. So it seems the ADC must do some interleaving internally for the 12 bit mode, but the datasheet is a bit confusing about this topic:
The high speed modes all utilize interleaving to achieve high sampling speed. Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves
4 ADC branches, while single channel mode interleave all 8 ADC branches. In precision mode interleaving is not
required and each ADC channel uses one ADC branch only.
So it seems ADC1 consists of 2 ADCs, and only one of them is used is precision mode (14 bit). This also corresponds with the reduction in spurs in 14 bit.
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