the developer referenced Andrew Holme's work. I built Andrew's system and it works great. I got lots of help from Andrew and Adrian Rus who went over the top to assist me.
I needed to use batteries for the runs in addition to low noise LDO regulators. Even with clean power supplies (and the LT3045 regulators) I still had some noise. So I'm surprised the performance is so good on this unit with USB power. Andrew's system only uses USB for control of the FPGA and then 1Gig ethernet for the data feeding the PC plotting system.
The expense is in the references, filters before the ADCs, the DAC oscillator and the shielding and positioning of the equipment in the lab. I had the best results using Dewalt 20v batteries stepped down with the LT regulators. Adrian made some mods to his ADC board that worked better for him. The other factor that came into play was the interaction of the ADC clock and the DUT as well as the reference oscillators. Adrian developed a spreadsheet that calculated the interaction of the reference, DUT and ADC clock but the bottom line is you want the harmonics and mixing to not produce a spur within the measurement range. I think that is an adequate explanation. the last reference oscillators I used were at 26Mhz made by Wenzel with Minicircuits filters at 27Mhz. Then I remember getting designs from someone for non-reflective filters. Most of this is on Andrew's site that which I highly recommend.
Adrian then sent me some other oscillator links that I was yet to implement though I acquired them. Given you don't need (or want) references at 10Mhz in many cases, you can move onto other odd frequencies like I did at 26Mhz. But I think the 26Mhz interacted with my ADC clock, so I then acquired one that is phased locked to 10Mhz but generates 118Mhz and change. You also have to setup the ADC to accept the correct clock (in Andrew's implementation) and it must be clean with low jitter. The limit on the ADC Andrew used was 125Mhz.
One other point, in order to get the maximum performance you need to bring the DUT and references up to the ADC limits. I ended up spending a lot of money on QB188 amps and attenuators. I used fixed attenuators as well as variable controlled by my HP70K system.
The bottom line is that to get to a clean -185 noise floor takes a lot of screwing around. But considering you can do it for substantially less money (under $2,000 for Andrew's) implementation assuming you get the SP605 spartan6 FPGA used, and it compares to units costing 10x that number, I thought it was a good deal. Andrew's unit didn't do ADEV work or interface directly with Timelab the last time I updated it. But you can dump the data into Timelab, matlab, Stable32, etc. I use another entire system for ADEV work anyway.
I never thought I could get that level of performance for such a modest price. You can get it going for under $750 USD and then build it up from there.
Jerry
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