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Rigol DSA815 dead LO for the 900-1500MHz range
TurboTom:
Wow, that's quite interesting! So the varactors can be driven up to ~32V maximum, which is beyond their specified reverse voltage of 30V but below the "maximum reverse voltage" with >5kOhms series resistance, which apparently is lower in the oscillator circuits (10 Ohms + 26.1 Ohms + whatever the source resistance of the charge pump interface circuit is).
Another peculiar detail is that the PLL IC that Rigol used in the DSA815 (ADF4169) is capable of generating "waveforms" in the frequency domain by itself, i.e. it can provide the frequency sweep without additional activity of the FPGA. That would easily explain the fast control voltage rise when the inoperational third oscillator branch gets selected and the PLL senses a "too low" frequency.
At the maximum varactor drive voltage, the capacity of the BB555 is round about 2pF, so the anti-series arrangement of two of these diodes result in ~1pF as a minimum. Parasitic inductance of the SC79 package is specified as 0.6nH. This matches G0HZU's figures quite accurately. :-+
Assuming that the three VCOs are operated over approximately the same control voltage range, we should expect someting like 7V @ 3.186 GHz and 20V @ 3.786 GHz.
G0HZU:
Yes, it's definitely getting more interesting now...
It's probably worth mentioning how this circuit will work in the large signal condition. Up until now, I've been looking at small signal 'start up' conditions.
Once the VCO starts up, the energy in the resonator will build and build and there will come a point where the increasing drive signal to the BFP450 base will cause the BFP450 to conduct on less and less of the RF cycle because it will be reverse biased for most of the RF cycle once the amplitude of the RF cycle becomes large. This means that the tradeoff between increasing drive level leading to reduced conduction angle will mean a form of equilibrium will be reached in the large signal condition.
You can think of the BJT as 'tapping' a brief burst of energy into the resonator once a cycle and this maintains equilibrium in the large signal condition. A bit like briefly tapping a bouncing ball to keep it bouncing up and down at the same amplitude every bounce.
I'm not sure what this means for the value of the series unknown cap C246. The value of this cap will influence the output power level of the oscillator, but if it is too big it will load the resonator during the crucial startup (small signal) phase.
It might be worth trying C245 as 2.2pF and then experiment with values from 0.8pF through to 1.5pF for C246. There is effectively a small amount of additional capacitance across the shunt C245 cap in the form of the square PCB pad that connects C245, C246 and one of the diodes and L218. So C245 may end up being a bit less than 2.2pF. I'm really just guessing until I model it all better.
The bias chokes L218 and L211 will presumably be chosen to be close to self resonance up at about 3 GHz so they should appear fairly invisible to the rest of the circuit. They might have a value of about 15nH for example.
G0HZU:
If C245 is chosen to be too large it will begin to isolate the BFP450 too much as it is part of a capacitive divider in the resonator. There is a double whammy effect here because of the package inductance of C245. This will make it look even larger up at 3.5 GHz. So none of this is a trivial task. It may well end up being a case of trial and error.
C246 needs to be chosen to give reliable startup (and correct output power?) and C245 needs to be chosen to achieve the target VCO tuning gain in terms of MHz/V. There will be some interaction between both caps and it looks like Rigol had to use select on test caps here. So don't expect to get it right first time even if someone knows the typical values for these two caps :)
TurboTom:
Here's the complete schematic of the highest frequency oscillator branch including the bias circuitry. Interestingly, Rigol uses the LED to bias the two current sinks for the base and emitter currents of the RF transistor. In order to disable the oscillator branch, this LED is simply shorted out to the negative supply rail by Q204. The zener D206 provides the level shifting so it can be operated from digital circuitry supplied by a positive rail. Via the emitter current sink (Q206) and R247, the corresponding PIN diode gets positively biased, so as soon as the selected oscillator branch gets enabled, the corresponding RF switch also conducts the signal. Neat and simple design!
P.S. Vee is probably in the ballpark of -5V, considering a 6.8V zener is used for level shifting, and assuming a 3.3V digital rail to power the FPGA I/O.
G0HZU:
That's a really useful diagram thanks!
I've added some waveform info to it as below. The green circle highlights the main resonator. At startup, some energy from this resonator goes into the BFP450 as a forward wave and because the BFP450 is a negative resistance generator, the reflected wave back out of the BFP450 will be in phase and slightly bigger than the forward wave.
After a very short time this energy gets filtered by the resonator into a sine wave at its resonant frequency and because more energy returns from the BFP450 than goes into it, the resonator starts building up more and more RF energy at the resonant frequency. Eventually, the BFP450 can't generate a 'bigger' reflected wave than the incident wave because it has hit its limits and this is when the resonator will have several milliwatts of power at the resonator.
The more power at the resonator, the better the phase noise and the more selective the resonator is (i.e. the higher its loaded Q) the better the phase noise will be.
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