Rigol HDO1000 and HDO4000 12bit oscilloscopes launched in China

[Martin72]

It also mentions a 16-bit "high resolution" mode. 

Yepp, with the common known restrictions (every scope have, to be fair).
12 Bit is enough...
The benefit you can see in this short video, really simple example made but the more it gets obvious:



Starting at 2:47

[coppice]

Recall some time ago when Fujitsu Microelectronics shocked the IC design world with their amazing 56 GSPS 8 bit ADC back in ~2009, that was the last we've seen of any significant ADC surprises, maybe there are others lurking in China that we aren't aware of!!

If you look at the presentation material for that device you'll see the actual ADC was not much of a technical challenge. All the complexity in the device is handling the huge flood of data.

I guess it's no big secret that if you want to build a very high-speed ADC, you probably need an RF sampler up front, a massive demux stage and then you just interleave a couple hundred slower ADCs. You can draw the basic architecture on a napkin. Well, and then you just need to solve the endless practical problems that come with it...  Like mismatch (gain, offset, timing) calibration, clock distribution/alignment, the concrete demux/subsampling/buffering topology. I think one of the current Keysight ADCs has a secondary SiGe die that is mostly buffers for signal distribution. Power/thermal budget will be also a big concern all the time. A lot of small things have to go right in order to have a low-noise, low-distortion output instead of a complete mess. Sadly, marketing material tends to focus on impressing potential customers, not on providing interesting technical details to would-be-competitors. 

At one point there was a detailed presentation on the web about the internals of that device. I seem to remember the weird thing was that they describe the ADCs as being SAR converters. I would expect them to be pipelined. Pipelined ADCs do perform a successive approximation, but they are usually described as pipelined, rather than SAR.

[mawyatt]

They used the capacitive ratio based SAR kind of like we had developed back in ~80 but much faster.

We had developed probably the 1st Capacitive Ratio DAC back then based upon charge redistribution in capacitor ratios, earlier DACs were based upon ratio resistors (classic R 2R) or ratio current sources, or both.

After the DAC development, we realized we could use the DAC in a SAR based ADC. Since we had a customer that wanted an ultra low power ADC, we utilized sub-threshold logic for the SA logic and created a somewhat unique ADC. It was floating point with 8 bit mantissa and 3 bit exponent (these were 10dB steps) and included a clock tracking anti-aliasing filter as well as a special low noise preamp and biasing network for a dedicated sensor. Analog Devices got wind of this development and wanted to license the core Capacitive Ratio SAR ADC, but our company wasn't interested in licensing (long story). Later this technique became useful in the CMOS imager ADCs, they are Capacitive Ratio SAR based, very effective and small area ADC which is exactly what was needed in CMOS sensors because they use one ADC per column on the sensor.

Fuji did something similar but instead of operating all the ADCs in parallel on the columns like the imagers, they operated them sequentially in a staggered fashion every ~15ps!!

This was quite a feat they pulled off back then, so hat's off to them in spite of the usage restrictions!!

Best,

[mawyatt]

Recall some time ago when Fujitsu Microelectronics shocked the IC design world with their amazing 56 GSPS 8 bit ADC back in ~2009, that was the last we've seen of any significant ADC surprises, maybe there are others lurking in China that we aren't aware of!!

If you look at the presentation material for that device you'll see the actual ADC was not much of a technical challenge. All the complexity in the device is handling the huge flood of data.

I guess it's no big secret that if you want to build a very high-speed ADC, you probably need an RF sampler up front, a massive demux stage and then you just interleave a couple hundred slower ADCs. You can draw the basic architecture on a napkin. Well, and then you just need to solve the endless practical problems that come with it...  Like mismatch (gain, offset, timing) calibration, clock distribution/alignment, the concrete demux/subsampling/buffering topology. I think one of the current Keysight ADCs has a secondary SiGe die that is mostly buffers for signal distribution. Power/thermal budget will be also a big concern all the time. A lot of small things have to go right in order to have a low-noise, low-distortion output instead of a complete mess. Sadly, marketing material tends to focus on impressing potential customers, not on providing interesting technical details to would-be-competitors. 

Although retired from IC design/layout mawyatt is still bound by NDA's. 
Sad it is too as there is so much to learn of his experiences in crafting the silicon we all use. 

Probably will forget anything the NDAs cover anyway, memory is fading fast

Well I can say that if you have hind sight of a decade and half, and have never designed an ADC chip, or a chip of this level, then sure it looks easy to one that doesn't have to actually do it or be responsible for such (read put up your own $). Landing a man on the Moon happened long long ago, and today everyone knows how to do it, and yet nobody's been back!! That was a incredibly difficult task back in the late 60s and still is today, in spite of all the advancements and "know how".

Same goes for the Fuji 64GSPS ADC, I know Keysight did it and what it took and they didn't do it in 65nm
BTW they did develop a custom SiGe BiCMOS chip front end for the DSO, because the pure CMOS wasn't good enough!!

Anyway, this is a little off topic, so let's all hope Rigol's new HD DSO is a jewel. Dave has one now, so soon we'll get a glimpse of this puppy and how well it performs, hopefully he'll perform a 2 tone IMD test

Best,

[BravoV]

With all the "speculations" throwing around ...

.. question is, why it is so hard to wait & see, until Dave tested and bench-marked this thingy ? 

[2N3055]

With all the "speculations" throwing around ...

.. question is, why it is so hard to wait & see, until Dave tested and bench-marked this thingy ? 

Because people have little patience and talk is cheap? 
People like speculating.

[EEVblog]

Probably will forget anything the NDAs cover anyway, memory is fading fast

We need to do that Amp Hour episode!

[EEVblog]

.. question is, why it is so hard to wait & see, until Dave tested and bench-marked this thingy ? 

Scheduled for delivery tomorrow.
Am I the only one who's got one?

[tautech]

Probably will forget anything the NDAs cover anyway, memory is fading fast

We need to do that Amp Hour episode!

Yep, like I emailed you a year ago !
Very pleased to witness you can now see what we have in mawyatt here.
IIRC I sent you his contact details.

[BravoV]

.. question is, why it is so hard to wait & see, until Dave tested and bench-marked this thingy ? 

Scheduled for delivery tomorrow.
Am I the only one who's got one?

Well Dave, do a quick and short video of unboxing and do a brief noise test, and resolution too, that hopefully will be easy and fast (compared to full test & teardown), this will cool down the not so patience audiences. 

[mawyatt]

Probably will forget anything the NDAs cover anyway, memory is fading fast

We need to do that Amp Hour episode!

Yes know we're delinquent

Certain "things" around here have prevented such and hopefully will be able to accommodate our commitment soon!!

Best,

[mawyatt]

Probably will forget anything the NDAs cover anyway, memory is fading fast

We need to do that Amp Hour episode!

Yep, like I emailed you a year ago !
Very pleased to witness you can now see what we have in mawyatt here.
IIRC I sent you his contact details.

We've committed to do such sometime ago, but things out of our immediate control have prevented this. As mentioned to Dave above, hopefully we'll be able to honor that commitment soon.

We've had such a great time discussing technology related things here, with such informative and knowledgable folks, that the commitment has now become an obligation

Best,

[Fungus]

Well Dave, do a quick and short video of unboxing and do a brief noise test, and resolution too, that hopefully will be easy and fast (compared to full test & teardown), this will cool down the not so patience audiences. 

Nah, just post a hint.

"Can confirm it's very low noise"

or

"Can confirm it's very, very low noise"

[2N3055]

Well Dave, do a quick and short video of unboxing and do a brief noise test, and resolution too, that hopefully will be easy and fast (compared to full test & teardown), this will cool down the not so patience audiences. 

Nah, just post a hint.

"Can confirm it's very low noise"

or

"Can confirm it's very, very low noise"

Those are meaningless statements without numbers and test methodology described.. How would he know without testing?

[Fungus]

How would he know without testing?

Dave? He just sticks his tongue out at the right angle and looks at it.

[EEVblog]

Well Dave, do a quick and short video of unboxing and do a brief noise test, and resolution too, that hopefully will be easy and fast (compared to full test & teardown), this will cool down the not so patience audiences. 

Nah, just post a hint.

"Can confirm it's very low noise"

or

"Can confirm it's very, very low noise"

Those are meaningless statements without numbers and test methodology described.. How would he know without testing?

Just arrived.
Another video conveniently has a snag, so can't progress on that right now.
Will unbox today and test before a teardown.
Noise would be measured with a 50ohm shunt on input, 20MHz bandwidth limit enabled, maximum memory depth and RMS and pk-pk measurements at say 1ms timebase.
Adjust to flavour.

[tautech]

Just arrived.
Another video conveniently has a snag, so can't progress on that right now.
Will unbox today and test before a teardown.
Noise would be measured with a 50ohm shunt on input, 20MHz bandwidth limit enabled, maximum memory depth and RMS and pk-pk measurements at say 1ms timebase.
Adjust to flavour.

No input Gnd coupling ?

[EEVblog]

Just arrived.
Another video conveniently has a snag, so can't progress on that right now.
Will unbox today and test before a teardown.
Noise would be measured with a 50ohm shunt on input, 20MHz bandwidth limit enabled, maximum memory depth and RMS and pk-pk measurements at say 1ms timebase.
Adjust to flavour.

No input Gnd coupling ?

Don't know yet.
But in any case I think the noise should be input-referred as ultimately that's all that matters.

[maxwell3e10]

It would be better to adjust memory depth to what just fits on the screen at maximum sample rate, say 10 msec @4GS/sec gives 40MSamples. Otherwise there is ambiguity how the scope calculates RMS (probably just screen range, not whole memory) and the effects of 1/f noise. Even better would be to download raw data so one can calculate the spectrum in noise density units.

18 uV rms at 20 MHz bandwidth corresponds to 4 nV/Hz^(1/2) - a good but not remarkable of level of noise, similar to Lecroy HDO4000 and not as good as R&S RTM3000, https://www.eevblog.com/forum/testgear/oscilloscope-input-noise-comparison/msg1967915/#msg1967915. For reference, a good LNA would have <2 nV/Hz^(1/2)

Another quick test would be to slowly increase vertical full-range scale until RMS noise begins to increase- this would test ENOB of the ADC.

[tautech]

Just arrived.
Another video conveniently has a snag, so can't progress on that right now.
Will unbox today and test before a teardown.
Noise would be measured with a 50ohm shunt on input, 20MHz bandwidth limit enabled, maximum memory depth and RMS and pk-pk measurements at say 1ms timebase.
Adjust to flavour.

No input Gnd coupling ?

Don't know yet.
But in any case I think the noise should be input-referred as ultimately that's all that matters.

Yes well there's input noise and system noise so you need examine both. 

[EEVblog]

Yes well there's input noise and system noise so you need examine both. 

Just tested it. System grounding software flat lines the display, no meaurement to be had.

As I suspected, the 100uV/div range is a 500uV/div range with the 12bit goodness. Under 1mV is bandwidth limited to 20MHz, again, no surprise there.

[EEVblog]

21uV AC RMS noise at full 250M memory 100uV range 1ms/div. No difference on 200uV and 500uV ranges because they are physically the same.
17uV at 1M memory which meets the 18uV spec.
Attached plot is with input internal 50ohm terminated. Same with 1M and external 50ohm terminator.
Curiously the measurement stats stop at 1000 samples.

[EEVblog]

Found a couple of quirks when zooming in the vertical, you'll see in the video, but it can lead to inaccurate screen and cursor measurements.

[EEVblog]

Annoyingly, I can't seem to find a way to turn of sinx/x interpolation, and it does it based on the stopped displayed data. So when you freeze waveform and then attempt to zoom in you can't get to see the quantisation level like I can on my R&S2000 I used a comparison

[Fungus]

21uV AC RMS noise at full 250M memory 100uV range 1ms/div. No difference on 200uV and 500uV ranges because they are physically the same.

Seems like they knocked it out of the park then.

(so far out that they added a 100uV range)