Rigol HDO1000 and HDO4000 12bit oscilloscopes launched in China

[voltsandjolts]

Screenshots overlay says HDO1204

[2N3055]

Screenshots overlay says HDO1204

 
I didn't register it...  I need more coffee...

Thanks!!

[Fungus]

HDO1000 series 50ohm terminated. No internal 50ohm, but it says that on the front panel, LOL!

So... it's awesome, but about 3x worse than the HD4000. 

I wonder where the difference is between the two. Is it internal vs. external 50 Ohm?

(or maybe it's done on purpose to sell more HD4000s )

[Fungus]

So the question is: How long before we see a new 2000 series with AWG, digital logic and this front end?

I guess they'll need some time to implement all the other stuff on the new Android OS.

PS: I just noticed this on their web site - a 3D view to show the captured waveforms over time. Replay them in 3D? Scroll through them to find the runts...?

[2N3055]

PS: I just noticed this on their web site - a 3D view to show the captured waveforms over time. Replay them in 3D? Scroll through them to find the runts...?

No you cannot do anything with it. Not even measurement can be enabled in that mode according to manual.. That is only visual mode..

[JeremyC]

HDO1000 series 50ohm terminated 1M point, 1ms, 500uV/1mV/1V

All files in the archive have .bin extension. Is it mistake?

RigolHDO1000-50ohm-1ms-1M-1V.bin
RigolHDO1000-50ohm-1ms-1M-1mV.bin
RigolHDO1000-50ohm-1ms-1M-500uV.bin

[maxwell3e10]

Dave, thanks, but I think this is without 20 MHz filter, so 50 MS/sec sample rate will get a lot of aliasing. Can you take data at full sample rate?

[Kleinstein]

It looks a lot like th 20 MHz BW filter is just a digital / software thing (rather steep initial drop and than stop band ripple) . Chances are a reduces sampling rate could as well go along with appropriate digital filtering. Chances are high the ADC would still run at it's maximum rate and the data are decimated in some way. The question is how the data rate is reduced. Especially with a low noise design it absolutely makes sense to have more than just sample skipping.
Besides the nose it many interresting to check if aliasing happens. A possible test would be with a test signal (e.g. 40 MHz) that would cause aliasing if no extra measures are taken when the data rate is reduced.

One may see some aliasing and higher noise when the actual sampling rate is reduced because more input channels are used.

[Martin72]

HDO1000 series 50ohm terminated. No internal 50ohm, but it says that on the front panel, LOL!

Damn, you´re right...
A teardown could show if there is a preparation for it in the layout...

[EEVblog]

So... it's awesome, but about 3x worse than the HD4000. 
I wonder where the difference is between the two. Is it internal vs. external 50 Ohm?

The HDO1000 won't have a 50ohm path, so I need to compare both on the 1M path with external 50ohm. Will do that today.

[Martin72]

I guess they'll need some time to implement all the other stuff on the new Android OS.

Let´s hope so.
In the last years since I got my first rigol it seems to me that they´re leaving their models "unfinished" and hurrying to their next project.

PS: I just noticed this on their web site - a 3D view to show the captured waveforms over time. Replay them in 3D? Scroll through them to find the runts...?

Some of our newer lecroys got this too, I could have a look what else you can do with it except it´s looking cool...

[nctnico]

PS: I just noticed this on their web site - a 3D view to show the captured waveforms over time. Replay them in 3D? Scroll through them to find the runts...?

Some of our newer lecroys got this too, I could have a look what else you can do with it except it´s looking cool...

Define new... The Lecroy Wavepro 7k I have can already create a 3D view of a signal. I can't imagine a use for it but no doubt Lecroy has a video that shows how and why a 3D view can be useful.

[Martin72]

We got Waverunners and HDOs with this "function", ordered 2019 therefore "newer".
(In comparison with our other waverunners they´re bloody young..)

[EEVblog]

FYI R&S have offered an MXO4 series, who wants to see inside it?

[EEVblog]

Confirmed, HDO1000 noise is the same as HDO4000 noise on 1mV (17uV) and 1V ranges.

[EEVblog]

It looks a lot like th 20 MHz BW filter is just a digital / software thing (rather steep initial drop and than stop band ripple) . Chances are a reduces sampling rate could as well go along with appropriate digital filtering. Chances are high the ADC would still run at it's maximum rate and the data are decimated in some way. The question is how the data rate is reduced. Especially with a low noise design it absolutely makes sense to have more than just sample skipping.
Besides the nose it many interresting to check if aliasing happens. A possible test would be with a test signal (e.g. 40 MHz) that would cause aliasing if no extra measures are taken when the data rate is reduced.

One may see some aliasing and higher noise when the actual sampling rate is reduced because more input channels are used.

40MHz input wiht 20MHz bandwidth limit just shows a reduced amplitude 40MHz signal.
No anti-aliasing though as a 10MHz input will show (and measure) 1Hz if you slow the timebase down enough.
For funsies:

[Fungus]

40MHz input wiht 20MHz bandwidth limit just shows a reduced amplitude 40MHz signal.
No anti-aliasing though as a 10MHz input will show (and measure) 1Hz if you slow the timebase down enough.

The filter has to be done in hardware. It would break all sorts of things if it was in software.

[coppice]

40MHz input wiht 20MHz bandwidth limit just shows a reduced amplitude 40MHz signal.
No anti-aliasing though as a 10MHz input will show (and measure) 1Hz if you slow the timebase down enough.

The filter has to be done in hardware. It would break all sorts of things if it was in software.

It has to be done in hardware for it to be useful. If the goal is simply to have a 20MHz mode for compliance with a customer's requirements list, well any old garbage will do.

[Kleinstein]

40MHz input wiht 20MHz bandwidth limit just shows a reduced amplitude 40MHz signal.
No anti-aliasing though as a 10MHz input will show (and measure) 1Hz if you slow the timebase down enough.

The filter has to be done in hardware. It would break all sorts of things if it was in software.

One needs some anti aliasing filter in hardware. However this does not have to follow a reduced data rate or the standard 20 MHz. Only aliasing for actual sampling rate of the ADC is to be avoided. The actual conversion rate of the ADC and the number of samples stored don't have to be the same.  It is well possible to keep the ADC running at the nominal speed (e.g. 2/4 GSps) and do the filtering to avoid aliasing from a lower data rate digitally on the high speed data together with decimation. This does need quite some computational power however (could be part of the ADC chip or in the main FPGA). So it is not clear if and when this is used. Some scopes offer this as averaging over consecutive samples as extended resolution mode. So it could depend on how the reduced data rate (shown as samples per second) is set. There may be a mode with aliasing and a different setting without aliasing.
If they incluse digital filtering, they could as well also use it for the 20 MHz and maybe the limited BW versions.

[maxwell3e10]

For reference, here is what the noise spectrum looks like using Dave's 50MS/sec data. It's about a factor of 3 higher than it should be because of aliasing from 10 times larger bandwidth. For HDO4000 data taken at 50M/sec but with 20 MHz bandwidth had approximately correct noise level, which indicates that filtering is done properly.

[Martin72]

What about the "enormous" peaks between 10khz and 100khz, where did they come from ?

[maxwell3e10]

What about the "enormous" peaks between 10khz and 100khz, where did they come from ?

Anywhere from n*25MHz

[Fungus]

40MHz input wiht 20MHz bandwidth limit just shows a reduced amplitude 40MHz signal.
No anti-aliasing though as a 10MHz input will show (and measure) 1Hz if you slow the timebase down enough.

The filter has to be done in hardware. It would break all sorts of things if it was in software.

It has to be done in hardware for it to be useful. If the goal is simply to have a 20MHz mode for compliance with a customer's requirements list, well any old garbage will do.

Are you serious? A hardware low pass filter is incredibly cheap to do - it's just a capacitor (plus a MOSFET to connect it to the input).

[David Hess]

40MHz input wiht 20MHz bandwidth limit just shows a reduced amplitude 40MHz signal.
No anti-aliasing though as a 10MHz input will show (and measure) 1Hz if you slow the timebase down enough.

The filter has to be done in hardware. It would break all sorts of things if it was in software.

One needs some anti aliasing filter in hardware. However this does not have to follow a reduced data rate or the standard 20 MHz. Only aliasing for actual sampling rate of the ADC is to be avoided. The actual conversion rate of the ADC and the number of samples stored don't have to be the same.  It is well possible to keep the ADC running at the nominal speed (e.g. 2/4 GSps) and do the filtering to avoid aliasing from a lower data rate digitally on the high speed data together with decimation. This does need quite some computational power however (could be part of the ADC chip or in the main FPGA). So it is not clear if and when this is used. Some scopes offer this as averaging over consecutive samples as extended resolution mode. So it could depend on how the reduced data rate (shown as samples per second) is set. There may be a mode with aliasing and a different setting without aliasing.
If they incluse digital filtering, they could as well also use it for the 20 MHz and maybe the limited BW versions.

Tektronix does it that way on their older DSOs and MSOs.  The bandwidth limit function includes both hardware and DSP options, and they perform slightly differently.  As far as I know the software bandwidth limiting occurs during decimation so the digitizers always runs at full speed, which is normal for all DSOs.  Filtering before decimation in real time requires considerable hardware computing resources, but that is getting cheaper all the time.

Doing the filtering in DSP before decimation is a variation of "high resolution" mode available on many DSOs.  High resolution mode is just boxcar averaging which is trivial to implement with shifts and adds at high speed, but makes for a poorly performing filter.  A finite impulse response (FIR) bandwidth filter requires multiply-accumulate.  Individual multipliers are not usually fast enough even now, but a parallel implementation of a FIR filter solves this.

[hhappy1]

Looking at Dave's hdo1000 video, it shows 2Gs/s when it's a single channel.
The data sheet was announced as 1Gs/s.

Did Dave upgrade it?