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RPL1116 (MSO1000Z) and PLA2216 (MSO5000) Active Logic Probe teardown

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thmjpr:
Can confirm the noise, even with the Logic analyzer completely disconnected, some channels seem to have injected noise and go wild. Wonder if a high value (100k) pull-down on the connector board would help to get rid of that. Seems odd that Rigol would leave it high-z.

Also confirm the original pinout of the connector has many signals flipped (D1, D3, D5, D7, D9, D13, D14, D15), see attached for what it should be. On mine, dumb luck meant I flipped one of the pinouts of the LM7324, so I only have these flipped: D3, D7, D14, D15. I'll think if I want to mod the main board or the pods to fix this.. Once I've done some high speed testing, can send out USBC boards if anyone wants the extras (knowing that you have to do some mods).

Noticed that 2V5 seems to get pulled down a fair bit, with just one pod connected I was reading 2.2V. Not sure what the wire gauge in my USB cables is.
Also if it wasn't clear (because I didn't realize this), the Vref is: -1.5 to +1.5 to represent a -15 to +15V trigger level. How I have it now, the STM32 can only read positive trigger voltages (0 to 1.5V).

Rerouter:
100% certain on D11 and D14? they break the pattern of all the others

TK:

--- Quote from: thmjpr on May 18, 2019, 03:55:27 am ---Can confirm the noise, even with the Logic analyzer completely disconnected

--- End quote ---
By completely disconnected you mean the minimum required for the Scope to detected and activate the logic analyzer, correct?  The microcontroller that was added for the LEDs, is it active when you detect the noise?

thmjpr:
See attached for 40MHz SPI signal on analog + logic input, seems to work quite well other than a bit of jitter.
One issue is there is a ~150ns offset between the analog channels at the top, and the same digital channel on the bottom. I'm thinking this is worth reporting as a bug.
One possible workaround for this would be adjusting the analog channel offsets, so all are -150ns. But that is a lot so it may not be possible.. will check.

Temperature is 55C on the chip and 45C on the bottom of the board (in open air at 23C). It will get a bit worse inside the case, but would likely be fine without a heatsink.


--- Quote from: TK on May 18, 2019, 06:24:16 pm ---By completely disconnected you mean the minimum required for the Scope to detected and activate the logic analyzer, correct?  The microcontroller that was added for the LEDs, is it active when you detect the noise?

--- End quote ---

Yeah thats right, nothing connected to the Rigols 50-pin port at all. Sometimes the LA will run for a bit, even after unplugging the pod (some bug or timing detection). But you can manually short pin 1 to ground too, to enable the LA and test this way as well. I suppose in Rigols design case it doesn't matter, as you either have all channels connected, driving the inputs hard, or not connected and LA disabled on the screen.
Good point about the micro though, I could see it having some effect.


--- Quote from: Rerouter on May 18, 2019, 07:46:47 am ---100% certain on D11 and D14? they break the pattern of all the others

--- End quote ---

It is an odd pattern, and it would make more sense if it was N, P, N, P repeating consistently. Actually now that you mention it, the bit order does have a "logical" pattern: if you skip two pins, it does go from D0, D1 .. to D7, and the same for D8 to D15. At first I thought it was completely nonsensical.

I will go over them again tomorrow now that I've modified my pod to swap D4 and verify the pinout (having the resistor pack made it easier, see photo below).

thmjpr:
With the pod now having D1 and D3 flipped, the signals D11 and D14 are still backwards. So they don't match the pattern seen on the other signals. To eliminate all possible sources of error it could be checked manually at the input pins.

Digital to analog delay cant be adjusted with ch-ch skew adjustment. This only delays the analog channel further forward on the x-axis (+/-150ns max). Maybe someone with the official logic pod can verify they see this digital-> analog delay as well. Adding a fixed offset in firmware would be nice, an adjustable offset in the menu even better still.

Channel to channel jitter is OK, I will get a shift back and forth of 1ns on D3, D2, D1 when triggering on D0 for example. Rigol spec is 2ns typical, 5ns maximum. Sample rate is 1GS/s at 200MHz, which all adds up.

Going to print the pod case again, font was too small to show up. Clear color would be cool too, to see the LED inside.
Adapter case coming soon.

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