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SainSmart DDS120 & DDS140 USB Oscilloscope
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doctormord:
 :-+ :-+ :-+

My testings with sigrok are not consistent at the moment. I thought, it should be fine to connect CLKOUT to CLK_ADC to have em running, but the readings makes no sense to me.

Mostly i get some 00 00 00 FF FF 00 FF garbage. This might be due to aliasing from the hostsides sampling frequency, as this could altered from 100k to 24M. Also the second port does not geive any results at all. Might be, that because the input multiplexer is not set valid and the corresponding output pin (FX2LP) is in tri-state. Couldn't check any further. Having another FX2LP logic-analyzer connected gives nothing valuable, as it is limited to 24M, so heavy aliasing in the results.
psynapse:
Doctormord,

When you talk of CLKOUT, I presume you mean pin 1 on the FX2.   IFCLK on pin 75, is the usual clock as you know.  I note that both CLKOUT and/or  IFCLK can be inverted under software control and that both can be prescaled.  So even if there is no difference in frequency, there will be differences in both skew and phase between the two.  And as you rightly say,  without a logic analyiser of 250Mhz or more, you will not be able to visualize the problem.

Have you measured the frequency on the two pins?  On the DDS140 these are fixed, ie once the firmware setup routine has run, these are static values.  If this is true for the DDS120 too, and both clocks run at 48Mhz, it suggests that your explanation that the FX2 subsamples the ADC (running at 48Mhz) at a 1/N rate, and in all probability this is achieved by reprogramming the GPIF wavetable.  If both these assertions are true, then the DDS120 is already delivering maximum performance, and the question becomes one of best firmware/software to support transfer.  If IFCLK is running at 30Mhz, flipping a bit in firmware should get you the performance you seek.  (The only way the DDS140 gets "more" performance is by buffering in the ADC values at 80Mhz into SRAM and then replaying them out to the FX2 FIFO at 48Mhz.  But that extra performance is at a high price)

So I have not given much help, except to say I think your analysis is correct.

Back to the FĂȘte
doctormord:
Yes, CLKOUT can be scaled (:1, :2, :4), while IFCLK is fixed to 30/48MHz when used as output. CLKOUT is always the same as Core-Clock, they share the same pin/divider. I need to measure CLKOUT to see what's going on. At 48MHz, the ADC would be slightly overclocked. But if this is true, they would advertise as 100Msps. :o
psynapse:

--- Quote from: doctormord on October 26, 2014, 01:18:32 pm --- At 48MHz, the ADC would be slightly overclocked. But if this is true, they would advertise as 100Msps. :o

--- End quote ---

Maybe even 200Msps  ;)

"ADC slightly overclocked" In the DDS140, and several rigol oscilloscopes the 40 meg part is overclocked at 80 or even 100Mhz.  It seems to work, although I expect badly.  The ADC is 5 bits of capacitive stages and 3 bits of flash,  I am taking this to suggest thay you might get 6 bits at 80Mhz

My 74lvc74s have arrived:- the trouble is that the are ssop (I had thought they were soic).  When I have good enough eyes to solder them,   I will measure the clock rates on the DDS140.

Ganzuul:

I have not had the time to look this weekend, but I had understood that the four buffers could be set up as a ring of four, one filling, one emptying and (in steady state) one full buffer waiting to be sent and the fourth empty buffer waiting to be filled.  I will look into it more.
doctormord:
I checked for the clocks at CLKOUT and IFCLK, they're the same at all times. Samplingfrequency does not affect anything, so the ADC and8051 are running at 48MHz all the time. Dunno if the phase-shift is important to note. (Blue is CLKOUT, Red is IFCLK)

(Only had a Rigol 1052E unaltered avail.)


--- Code: ---Analog Ch  State   Scale    Position   Coupling  BW Limit  Invert
CH1        On      1.00V/   40.0mV     DC        Off       Off
CH2        On      1.00V/   -2.04V     DC        Off       Off

Analog Ch  Impedance   Probe
CH1        1M Ohm      10X
CH2        1M Ohm      10X

Time    Time Ref    Main Scale    Delay
Main    Center      5.000ns/      -409.3000ns

Trigger  Source      Slope    Mode      Coupling     Level    Holdoff
Edge     CH2         Rising   Auto      DC            1.12V   500ns

Acquisition    Sampling    Memory Depth    Sample Rate
Normal         Realtime    Normal          500.0MSa   


--- End code ---
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