Products > Test Equipment
SainSmart DDS120 & DDS140 USB Oscilloscope
doctormord:
Well Doctormord is right about the ADC, the DDS120 and DDS140 (without modification) will do no phase shifting between their two inputs. However Ganzuuls observation is an interesting one. I have not looked at the analogue front end too much ..... Doctormord and Ganzuul are certainly more hardware capable than me. The only thing I would note is that for the designers of these scopes, wouldnt it have been easier to use antiphase clocks to the ADC ..... Having a tuned circuit to adjust costs money!
Well, this will work when we could antiphase IFCLK. Then we split the clocks and enable data-align on the ADC. Would be just a minor patch. We might also use one of the free multiplexer to parallel the inputs then. Switching needs to be done via an additional command (GPIO) within the custom firmware.
BTW, Doctormord, I have done some calibration of the analogue front end .... and found what you already knew. Significant 0v offsets and appalling gain variability. Now that I have (software) corrected these I need to look at gain nonlinearities .... have you taken that subject further since you mentioned your concerns?
Haven't looked into this yet, but would consider changing the multiplexers to types i mentioned earlier. I asked an application engineer within the company i work (as student). The problems concerning gain variance wouldnt be that important if the multiplexer resistor construction got implemented the other way around.
Means:
Resistor -> Multiplexer = bad
Multiplexer -> Resistor = good
It can easiliy be unterstood if you see the setup as an voltage-divider.
And a quick question. I am proposing to buffer INT5 with an opto, collector tied to +3v with a 10k resistor. Do you see problems with that?
Should work:
FODM8071
SFH6701/11
You might also consider TIs high speed digital isolators.
Once I have considered carefully how to implement a hardware trigger, that is next on my list.
Hardware-trigger should also be possible in DDS120.
psynapse:
Doctormord,
Have been building my hardware add-ons, so I have been quiet (as has everybody!)
In the process I took my DDS140 apart, again, and took the opportunity to trace through a bit more circuit. The ADC in the DDS140 has the clock pins and the S2 pin controlled by the CPLD, so it seems very probable that the DDS140 properly interleaves the two ADC in order to get its top sampling rate. This doesnt help DDS120 owners of course, but it means your mods can be DDS120 specific, which might make the job easier.
Tracing through the circuit, The external connector is as follows.
C1 + 5v
C2 PE 1 (clk)
C3 PE 0? with RC
C4 PE 3
C5 PE 5
C6 CLKOUT via 300 ohms 48Mhz
C7 -gnd
C8 - +3v3
C9 -DataB 7
C10 -DataB 6
C11 -dataB 5
C12 -dataB 4
C13 -dataB 3
C14 -dataB 2
C15 -dataB 1
C16 -dataB 0
Bn no pins
A1 -Gnd
A2 -Gnd
A3 -
A4 -
A5 PE 2
A6 -gnd
A7 -
A8 -gnd
A9 -
A10 -
A11 -
A12 PE 4
A13 -
A14 -
A15 - gnd
A16 - gnd
PE3,PE4 and PE5 seem to function as an I2C interface for controlling the waveform generator.
doctormord:
Regarding:
http://www.cypress.com/?docID=48811
Page 221
IFCLK can be inverted to internal CLK, so driving the ADC in "double-speed" is def. possible with a new firmware or a byte-patch in the existing one.
This might get helpful:
http://www.cypress.com/?docID=50815
psynapse:
Just a brief update for the DDS140. Bit PC.6 (fifo full) acts as a exact indicator of when data sampling is taking place (ie active low), except as noted below. PA.7 (go) shows when the host PC has demanded data acquisition , but is less exact .... in particular the back porch (ie after the fifo is full) is only cleared after the host PC has issued a code 50 (fifo status command). See the attached traces for a bit more detail. Data acquisition is shown for two capture rates 10M and 625k. Note that in both cases the Sainsmart PC software takes slightly over 100mS to re-issue the go code.
In mode 94 0A (240khz) on the DDS140, the fifo (more exactly the CPLD fifo) never shows full. Another reason to believe that the 94 0A mode on the DDS140 functions exactly as the DDS120 normal mode, ie ADC data direct into the FX2 fifos, and not via the cpld pseudo fifo.
So now I have my "trigger out", which shows when the data sampling window is open. Quite simply fifo not full on PC.6. I will now write a very short ISR for INT5 which will assert PA.7 and the allow normal software to detect when the fifo full flag changes (existing command 50). This will give me trigger in, though sadly not a pre-trigger in.
doctormord:
Nice!
Isn't pretrigger "just" a thing of implementing software "prebuffer"?
(Like on cameras)
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