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| SainSmart DDS120 & DDS140 USB Oscilloscope |
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| doctormord:
Wow, long time since i where in the circuit. As "psynapse" pointed out here: https://www.eevblog.com/forum/testgear/sainsmart-dds120-usb-oscilloscope-(buudai-bm102)/msg535995/#msg535995 with the internal switch resistance, its going like this by combination of bits. --- Quote ---OK I have looked a bit more at the circuit and the internal resistance of the 4052 is critical. Allowing internal resistances of 380,500 or 400 ohms for the three states, Q2 is programmable to have a gain of 2,3 or 5 (1+(620+380)/1000), (1+ (1500+500)/1000), (1+(3600+400)/1000) Odd gain figures, except we are driving the ADC differential, the other side being 1, the output of the unity gain buffer. So what the ADC sees is 2-1, 3-1 or 5-1 .... aka 1,2,4 .... It is kind of sweet in a chear cost cutting sort of way. A quick LTspice confirms So in summary, J3 is giving divide by two or divide by 10 (and if the divide by 2 is diode clamped, de facto divide by 10 is too) Whilst J9 gives multiply by one, two or four Put both together and you have, for the front end gain x2 x1 x0.5 x0.4 x0.2 x0.1 --- End quote --- So to sum this up: #Channel A: PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB #Channel B: PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB |
| merbanan:
This is the function I need to re-implement for the SainSmart http://sigrok.org/gitweb/?p=sigrok-firmware-fx2lafw.git;a=blob;f=hantek_6022be.c;h=8a73cc07b4ac74828f5303e1f1b7861dd1149cca;hb=189db3d41e4c3d8a4aec5ec605c03df75577d531#l190 With your latest info it will be straight forward. The only thing left is to figure out how to address the PEx pins and implement a new command for AC/DC coupling. And how to output the square wave pulse. |
| doctormord:
I wonder if clock setting is working, as the DDS120 is using the IFCLK output: --- Quote --- --- Quote from: doctormord on October 23, 2014, 04:26:38 pm ---Regarding the EZ-USB Technical Reference Manual: http://www.cypress.com/?docID=48811 page 125, the IFCLK can only output 30/48MHz from its internal source. (I must review the trace at IFCLK and CLKOUT.) Maybe its like: 24Mhz crystal -> PLL (48Mhz) -> /2 divider -> 8051 Core + CLKOUT [pin out] (24Mhz) -> IFCLK [pin in] + ADC_CLK (24Mhz) Then the 8051-Core, FIFO, and ADC are running at 24Mhz at all time. Sampling is then done by 1/1 (24MHz), 1/10 (2.4MHz), 1/100 (240kHz). From the specs, this scope should do 50Msps, but only when using both channels - single channel is 25Msps. This can't be true with a 24Mhz clock-source in no way, so we'll end up at 24/48Msps like Hantek. Even the software is lying to us when showing "50MHz" (should be "48MHz" -> 24MHz x 2 Channels) Conclusion: 50Mhz -> 48MHz == 24MHz x 2 Channels = 24Msps per Channel 2.4Mhz == 2.4MHz x 2 Channels = 2.4Msps per Channel 240kHz == 240kHz x 2 Channels = 240ksps per Channel The lower samplerates just skip sampling by 1/10, 1/100. ??? --- End quote --- --- End quote --- |
| doctormord:
--- Quote from: bianchifan on March 14, 2016, 08:48:04 am --- It works for me, just even tested. Nevertheless an alternative: https://mega.nz/#!pgdHHQIY --- End quote --- Needs the mega decryption key. :-// |
| merbanan:
--- Quote from: doctormord on March 15, 2016, 11:25:15 pm ---I wonder if clock setting is working, as the DDS120 is using the IFCLK output: --- End quote --- I just assumed it used the same as the Hantek. Tracing the pin on http://sigrok.org/wimg/d/d8/Hantek_6022be_pcb_top.jpg and http://sigrok.org/wimg/0/05/Hantek_6022be_pcb_bottom.jpg it looks to me it is connected the same as the SainSmart. (The signal goes through R35 and on both sides of the pcb and under the chips). |
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