Products > Test Equipment
Should I buy a Rigol MSO5000?
ebastler:
--- Quote from: TK on April 05, 2019, 05:40:38 pm ---It is something like what is happening with Keysight with their ASIC and the sample memory being too small..
--- End quote ---
Whereas, if it were an FPGA-based design, they would simply update the firmware to add more memory to the FPGA? 8)
I think there is no point in trying to spread FUD about the 5000Z.
What are you trying to achieve here?
nctnico:
--- Quote from: ebastler on April 05, 2019, 05:46:45 pm ---
--- Quote from: TK on April 05, 2019, 05:40:38 pm ---It is something like what is happening with Keysight with their ASIC and the sample memory being too small..
--- End quote ---
Whereas, if it were an FPGA-based design, they would simply update the firmware to add more memory to the FPGA? 8)
I think there is no point in trying to spread FUD about the 5000Z.
What are you trying to achieve here?
--- End quote ---
You are not getting the point TK is making. If you leave features out of an ASIC then doing a redesign will take a lot of time and money. The way the MSO5000 sits now makes it look like Rigol has left several important features (like decoding and high-res) out of the ASIC. Keysight has a different but equally severe limitation with their ASICs: they have a lot of functionality inside the ASIC except memory. That is very hard to fix/extend without a re-design. In case of an FPGA adding more memory or resources is easy: put a bigger FPGA on the board and/or use a larger memory chip.
To make matters worse for the Rigol MSO5000: the memory depth is so large that the processor doesn't have enough power to do any meaningful operations on the entire memory without slowing down to a crawl. With great memory comes a great need for processing power. Oscilloscopes with far less memory are already struggling to do software based operations on the acquisition memory (even though they are based on the Zync architecture). IMHO Rigol's ASIC doesn't give any edge over the competition but must have cost them a boat load of money.
rsjsouza:
--- Quote from: TK on April 05, 2019, 05:40:38 pm ---The maturity issue with the new Rigol scopes is a different matter... as they took the ASIC route, (...)
--- End quote ---
Rigol is new to the ASIC game, thus they will need some time before they get all kinks solved. Regardless, ASICs are not the same as they were - SW nowadays plays a much larger role than when HP released the first MegaZoom ASIC several decades ago. A modern ASIC usually has a multitude of small programmable units inside (albeit quite simple and tied to specific peripherals) and with a certain degree of re-routing and reconfigurability.
--- Quote from: ebastler on April 05, 2019, 05:46:45 pm ---
--- Quote from: TK on April 05, 2019, 05:40:38 pm ---It is something like what is happening with Keysight with their ASIC and the sample memory being too small..
--- End quote ---
Whereas, if it were an FPGA-based design, they would simply update the firmware to add more memory to the FPGA? 8)
I think there is no point in trying to spread FUD about the 5000Z.
What are you trying to achieve here?
--- End quote ---
I think TK is just showing a datapoint that happened with HPAK many decades ago.
ebastler:
--- Quote from: nctnico on April 05, 2019, 05:59:04 pm ---You are not getting the point TK is making. If you leave features out of an ASIC then doing a redesign will take a lot of time and money. The way the MSO5000 sits now makes it look like Rigol has left several important features (like decoding and high-res) out of the ASIC. Keysight has a different but equally severe limitation with their ASICs: they have a lot of functionality inside the ASIC except memory. That is very hard to fix/extend without a re-design. In case of an FPGA adding more memory or resources is easy: put a bigger FPGA on the board and/or use a larger memory chip.
--- End quote ---
Thank you, I understood the point alright. TK was claiming that the problem with ASICs is that "some limitations or bugs will never be resolved for a scope that was already sold". And then proceeded to give an example that would have required a hardware addition in any case, whether ASIC or FPGA-based.
Regarding the advantages of upgrading to a larger FPGA (in a revised scope generation) vs. re-spinning an ASIC which you claim, I'd say:
* Releasing an updated scope with enhanced hardware (FPGA) specs seems quite uncommon indeed. Can you name a few examples where manufacturers -- whether Chinese or US brands -- have done so?
* You may be overestimating the NRE cost for re-spinning an ASIC. See here for example. http://blog.zorinaq.com/asic-development-costs-are-lower-than-you-think/
Noy:
MSO5000 is not the first scope with this asic.
So i would worry more if i bought the 7000 series.
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