Products > Test Equipment
Show us your square wave
0culus:
Here's a frequency domain 10 MHz square wave from my 3325B, showing the harmonics tapering off in power out to around 330-340 MHz. :)
dzseki:
--- Quote from: joeqsmith on February 24, 2019, 05:11:01 am ---Looking at the manual, are they saying <1.5ns for the edge rate?
http://www.emg.hu/gepkonyvek/EMG_12563.pdf
--- End quote ---
That is for the trigger output, for the main output they say <1ns.
Here is a fresh shot, although my HP 1720A does not feel very well today...
The first rise is the trigger output of the EMG 12563, the second rise is the main output, the time base was set to 2ns/div. Unfortunately even the main output is measured beyond 1.6ns this time.
Anyway the trigger rise time is not that far behind, and considering that it also has a selectable amplitude between 1V (in reality 1.5V terminated) or 100mV and a fixed 50% duty cycle it is very much usable even alone.
MarkL:
Here's something a little different.
Here's a picture of the eye scan tool on an Agilent 16702B logic analyzer with a 16756A analysis card and E5382 probe. It's looking at the output of an Analog Devices SiGe ADCMP580 comparator eval board.
The ADCMP580 has a rise/fall of 37ps (typ.) for 20% to 80%. Applying a simple extrapolation puts it around 50ps for 10% to 90%.
The eye scan has a slope tool which I've placed at 10% and 90% in the center of the transition area. The time difference between the two markers is 130ps.
So, that would give the analyzer an estimated rise time of sqrt(130ps**2 - 50ps**2) = 120ps, and a BW somewhere around 2.9GHz. The analyzer datasheet says 2.33GHz, so I guess it's not too far off.
It works but it makes a really lousy sampling oscilloscope. It took several minutes to gather all these data points (180M samples, if I'm reading the stats right). The clock rate was 100MHz.
David Hess:
That reminds me of the testing I did adding a pretrigger to my PG506. The fast rise output shown below was taken with a Tektronix 7T11A in sequential sampling mode and a 14GHz S-4 sampling head through 1 or 2 nanoseconds, I forget, of RG400 cable on a analog storage 7834 mainframe. The photograph was processed to produce inverse gray scale to make it suitable for printing.
The edge itself is almost perfect with a transition time of about 550 picoseconds. This particular S-4 sampling head suffers from excessive blow-by this is not visible at this time scale. The tilt may be due to dribble up in the RG400 cable; I did not notice it at the time or I would have verified if that was the case.
The massive amount of pattern dependent jitter is caused by supply voltage variation caused by the TTL counter chain inside the PG506 getting into the TTL based 75 nanosecond pretrigger delay circuit. This was unnoticeable on a typical oscilloscope of up to 300MHz bandwidth; a 500MHz DSO might just see it. This circuit would need to be corrected to be usable for its intended application but it serves as a lesson as to why single ended logic including CMOS is not suitable for low jitter applications.
The second photograph was taken much later and is the same output being used to test my 100MHz 2232. The displayed aberrations are typical and produced completely within the oscilloscope and within the specifications although I think the performance could be improved slightly.
Keysight DanielBogdanoff:
So, not infinite bandwidth but...
how about 3.5 ps edge @ 113 GHz realtime bandwidth? >:D :popcorn:
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