DC Electronic Load able to simulate capacitive loads?

[rx8pilot]

Hi all, I am trying to understand how to better test some of my power supplies and efuse circuits. I have an inexpensive ARRAY electronic load and a custom built resistor bank. These devices work well for studying thermal management, efuse break points, efficiency, etc. but don't help much when it comes to driving capacitive loads with large inrush currents.

When designing electronic circuit protection, capacitive loads are a significant challenge. It's easy enough to make a circuit disconnect if it goes over a preset current limit, but a low ESR 1000uf capacitor on the the front end of a load can be 10x the break current during the inrush period. To avoid false trips, you have to design in some over-current delay. Exactly how much delay is what I need to know. After I get the design complete, I need to verify each and every output during production. That last requirement is the hardest one since it needs to be operated by low-level technician and hopefully log the results.

I am hoping to find an electronic load that can simulate the inrush current and decay of various capacitors. I have seen some of the higher-end models with adjustable rise time. To make it useful, I would need to program the dv/dt (rise time similar to a capacitor) and model a realistic decay that mimics the capacitor reaching its full charge and settling into a constant load.

Has anyone seen an electronic load that can do such a thing or should I stick with the more manual process of putting capacitors into my resistive load bank. That is such a coarse method.

[doctormord]

You may use something called a "capacitance multiplier".

[robrenz]

A bipolar operational supply like a Kepco BOP or EMI BOSS might be able to give you what you need by driving them with a arb wave generator to get the dv/dt and decay you are after.

[babysitter]

Turn the manual process of adding capacitors into a automatic one!

Get capacitors in quasi-binary stepping in the range you need, use a set of toggle switches or a computer-controlled relay box to select the right combination. This box goes between your load and source.

 A computer controlled unit can give you either selection of capacitance or some calculations on the fly which capacitance setting is the right one for your slope. Something that I would outsource to something as simple as either a PC with a USB relay card or even an Arduino "for street cred" 

[rx8pilot]

Thank you all. The ideal solution would be one that I can buy off the shelf. At the moment, I am under pressure to finish a specific project so taking on the design and creation of test equipment might have me looking for another line of work 

A bipolar operational supply like a Kepco BOP or EMI BOSS might be able to give you what you need by driving them with a arb wave generator to get the dv/dt and decay you are after.

I may be missing something on this one, but are you suggesting to use this configuration to test ability for a new power supply to drive a capacitive load?

I guess if nothing off the shelf is available, I could build something. It seems that this would be a common scenario that someone has built a box for at some point.

[babysitter]

I see some difference in philosophy here 

I would gladly get a hammond box, some caps, toggle switches and a terminal block, let the trainee solder, set up a operating procedure and qualify instead of buying a dedicated box with maybe way too many bells and whistles and learn to program it and all its quirks.... of which there may be many. Why emulate a capacitor in software and use a fragile digital controlled power stage to behave like one if you can buy a real capacitor cheap ?

[robrenz]

Thank you all. The ideal solution would be one that I can buy off the shelf. At the moment, I am under pressure to finish a specific project so taking on the design and creation of test equipment might have me looking for another line of work 

A bipolar operational supply like a Kepco BOP or EMI BOSS might be able to give you what you need by driving them with a arb wave generator to get the dv/dt and decay you are after.

I may be missing something on this one, but are you suggesting to use this configuration to test ability for a new power supply to drive a capacitive load?

I guess if nothing off the shelf is available, I could build something. It seems that this would be a common scenario that someone has built a box for at some point.

These are capable of sinking so they can be used as a dynamic Eload. Think of these as a mega opamp and you supplying the proper drive signal to get the loading you want.

[rx8pilot]

Whoa, did not get that at first. So I can input a waveform and it will sink based on the waveform at its input? Sounds too easy ;-)

I just found a Chroma family of products 63600 that may be able to do what I need although they are definitely a financial commitment.
http://www.chromausa.com/dcloads/63600-dc-load.php

Going back to the Kepco site to understand more......

[rx8pilot]

The Chroma 63600 series will most likely be a solution if I am willing to part with the money. Fingers crossed that a more affordable solution presents itself. As babysitter said, these things come with a mountain of bells and whistles. On the upside, I can delicately manipulate the parameters of resistance, inductance, capacitance to identify the limits of power supply designs.

[MarkL]

Hi all, I am trying to understand how to better test some of my power supplies and efuse circuits. I have an inexpensive ARRAY electronic load and a custom built resistor bank. These devices work well for studying thermal management, efuse break points, efficiency, etc. but don't help much when it comes to driving capacitive loads with large inrush currents.

Some Array loads, like the 372x series, have a programmable list of load values with up to 350 steps and a per step dwell time as little as 10us.  If you're trying to simulate an in-rush event, you could put together a current curve using short intervals of tapering CC settings.  Or you can use other modes, like CV, CP, or CR if that makes more sense for your test requirements (mode is settable on a per step basis, so anything goes).

Between transitions there's also a settable slew rate from 1mA to 3A per microsecond that you could use to your advantage.

The Array 372x is in the US$700 - US$800 range.  Don't know how that compares with the Chroma.  I know Kepco BOPs aren't cheap.

Many DC loads already have some sort of programmable high-speed list capability, and may be in the one you have?  Is it insufficient?

[rx8pilot]

I have the Array 3710, which is very basic. It works well for step programming in coarse time increments of 1sec, far too slow to build a curve for capacitors. Not sure if the 372x series could do it or not, although it appears that they have smaller steps. As much as it would be a drag to pay $3k+ for the big boy solution, it would be worse to buy the $800 solution and then the $3k solution. I am in the process of measuring and calculating a specification for the problem - actual di/dt which would be helpful.

It looks like the Kepco BOP or the Chroma could be the shortest path to success without having to guess too much. Both of them are north of $3k, which I may suck-up and do it. At the moment, I am largely relying on real loads that are VERY high value to do the final testing. The goal is to record a power profile for the devices and map that profile to an eLoad so I can beat the circuit to death and beyond without fear.

[babysitter]

Oh, did I just see that goalpost move the tiniest bit? 

You just need to go to real loads that are of very low value. Again sounds like a box, or several depending on the number and similarity of the profiles, with some R and C and maybe a 555 and MOSFET inside.

[nctnico]

Not quite what you are looking for but another suggestion:
What I have found an interesting test for power supplies is a DC load which uses transistors instead of MOSFETs and no current control feedback loop (which isn't really needed). A transistor nearly acts as an ideal current source (or in this case sink) which generally makes a power supply with poor loop control sing like a bird. Building another one (I wrecked the first) is still on my TODO list.

[Christe4nM]

I read this topic yesterday but wasn't able to post a reply then. I see you've already found the Chroma 63600. I was going to suggest you look into that one. As far as I know that's the only DC load that has built in signal processing to behave like a complex impedance. BTW, Apart from the full rack sized mainframe there is also a smaller mainframe  for two modules. I don't know if you could use a single module without a mainframe.

[macboy]

How about a low value resistor in series with a PTC resistor? At startup, when the PTC is cold, the inrush current will be high, limited by load R. Somewhere between milliseconds and seconds (or minutes) later, the current will drop to a steady lower point, limited by the PTC. The inrush, the time, and the steady state current will be determined by your choice of load R and PTC.

[robrenz]

Whoa, did not get that at first. So I can input a waveform and it will sink based on the waveform at its input? Sounds too easy ;-)

Going back to the Kepco site to understand more......

In this thread I show the EMI BOSS units being driven by a SG and also acting as an Eload.

[Kevin.D]

About 12 Months ago  I  did a rough outline design of an eLoad  to do just this type of thing, it uses a bank of mosfets ( 6 in a H+2 bridge)) first to  drive and characterize and then simulate reactive loads, the idea was to make an eLoad that could emulate  any of the common various reactive load's like small motors,tranformers etc.
 But It's a large hobby project and I just wasn't able to  find the enthusiasm to commit myself to building it (prob about 12-18 months project  and there would be alot of software involved which I dont particularly enjoy doing  ).
I got it In the 'maybe someday' project queue  .

Anyway back on topic with only what you asked to do is much less work though, you can modify any eLoad which does it's Constant Resistance mode in analogue loop (some use digital  processing for both CP and CR modes, so not them ones).
Because the common analogue  CR type circuit youl see can also function as a Constant/Variable  Z loop. So what you want to do can be as simple a mod as calculating the required cap to put across the top resistor of the main CR Set divider of the CR cntrl loop.

[TunerSandwich]

explain further.....you need to drive a purely capacitive load?

This is not possible, as all device inline have an ESR. 

If you are trying to characterize inrush slopes, against a turn on event....then you are making things a bit over complicated. 

How fast of a rise time do you need to measure?  There are some very easy ways to do this, and you don't need anything all that complex. 

What is the device under test?  Also what is the most common load presented to the device? 

There is some info lacking here....

I know I can fully characterize inrush events with my Maynuo DC load, and the PMA software in my scope.  Although even that is a bit luxurious. 

Are you looking to simply characterize inrush ?  or do you need to see a capacitive discharge curve, under load? 

Part of the problem here is that the device/load is going to have reactive properties of it's own, that need to be characterized and subtracted from the final outcome.....

every load I have tested has at least a minimal input capacitance of it's own.....as do the test leads.....

also what kind of bandwidth attenuation (freq vs. impedance) are you expecting to measure?  A 1000uF cap is going to be quite on the low side of plane impedance vs. frequency (step response), but you might be missing HF events that are sneaking through, as large inrush spikes.....those events can also couple back into the control loop and cause an oscillation.  Part of the problem with an active (external) load, is that it's going to ultimately inject some feedback into the test. 

Also what kind of power are we talking about here?  1 volt into a 0.01 ohm resistor is easy.....12 volts into the same is not....

There is also going to be HF ringing, that is in harmonic intervals to the primary/fundamental transient.....those artifacts are going to be delayed, in comparison to the fundamental....and they will be orders of magnitude above/below the switching frequency.....even if the PSU is linear, the turn on event will still exhibit these properties. 

DC is a myth 

50KHz is the sweep limit on those Chroma units.....yokogawa also makes some gear for characterizing such things....but again it's mostly LF limited.  Most of this stuff is designed for testing higher voltages....where currents are far lower......but dealing with 12v 3v 5v rails (I have to assume you make ATX style PSU's?) can call for currents that most of these products can't deal with.  I picked the specific Maynuo I acquired, because it was about the only DC load out there that would handle 60 amps, and still maintain usability, bench top form factor, sane pricing etc....

A 1000uF is going to have a planar impedance vs frequency of roughly 0.010 - 1 ohm at 0.01 HZ- 100 MHz.....I think you can see where a 50KHz sweep might limit fully characterizing impedance curves


The biggest problem I see here is that these loads are SIMULATING ideal and narrow tolerance ranges.  The best option to actually test yield (production units) is to physically characterize the real device.  For example I deal with some loads that are dynamic, varying with temperature (Ti alloy resistance wire) and the Maynuo load can get me part of the way there, but can't allow for tolerance in the production resistor.  The way I do this is by sweeping the load in the Maynuo, and then trying to subtract the properties added by the load itself. 

It's critical to understand the full scope of what loads might be presented to the PSU....both in a static and dynamic sense.  I have to assume these are all fast step responses.....and we are talking about cyclical transients below 2ms?
 

[rx8pilot]

Some additional details....

In the design phase of an eFuse circuit as well as DC/DC converters, I need to be able to understand the current profile of the loads. This part is fairly straightforward. Because I have no control over what gets plugged into my circuit, I have gathered a reasonable representation of what would be typical. Some if these loads have big inrush currents that can be 7x the trip level. These loads are generally designed for remote field operation from a wide range of power sources. Because of that, it is typical to see a lot of filter capacitors on the front end. The goal is to design an over current time delay that can deal with the inrush while still appropriately protecting the circuit from a dead short or long term overload. At this time I have delay as well as an absolute max of 10x the trip point. Some of the loads are very expensive (some are $100k+), so power cycling them over and over during design is a significant risk and better left to a piece of test equipment. That is why I am simply capturing the the start-up current profile of the real devices and saving the results.

So, my circuit (DUT) has multiple outputs and multiple voltages driving these loads. I need to be able to simulate some power-on inrush profiles so that I can see what scenarios will fail the circuit. When it is time to produce these, I need to be able to do 100% load testing including the various worst-case inrush profiles. This is also relevant to the output of the my DC/DC converters. Some of them seem like great performers with a gentle start-up, but when they need to start a load with 5000uf+ in the front, they might struggle and need more work.

In the end, the loads will almost always be some sort of switching supply with a lot of capacitance on the front end. I hope this is enough info to be useful. I had to rush through this post.....

Thank you so much for all the responses!

[TunerSandwich]

Some additional details....

In the design phase of an eFuse circuit as well as DC/DC converters, I need to be able to understand the current profile of the loads. This part is fairly straightforward. Because I have no control over what gets plugged into my circuit, I have gathered a reasonable representation of what would be typical. Some if these loads have big inrush currents that can be 7x the trip level. These loads are generally designed for remote field operation from a wide range of power sources. Because of that, it is typical to see a lot of filter capacitors on the front end. The goal is to design an over current time delay that can deal with the inrush while still appropriately protecting the circuit from a dead short or long term overload. At this time I have delay as well as an absolute max of 10x the trip point. Some of the loads are very expensive (some are $100k+), so power cycling them over and over during design is a significant risk and better left to a piece of test equipment. That is why I am simply capturing the the start-up current profile of the real devices and saving the results.

So, my circuit (DUT) has multiple outputs and multiple voltages driving these loads. I need to be able to simulate some power-on inrush profiles so that I can see what scenarios will fail the circuit. When it is time to produce these, I need to be able to do 100% load testing including the various worst-case inrush profiles. This is also relevant to the output of the my DC/DC converters. Some of them seem like great performers with a gentle start-up, but when they need to start a load with 5000uf+ in the front, they might struggle and need more work.

In the end, the loads will almost always be some sort of switching supply with a lot of capacitance on the front end. I hope this is enough info to be useful. I had to rush through this post.....

Thank you so much for all the responses!

Oh that is easy....just apply a delayed PG signal....as long as you understand the total transient window, you can pretty easily bypass the fuse, and then bring it back online with the PG signal.  Your regulator can have a delayed ramp on/off or a brick wall shut-down....based on the PG signal it sees. 

The best way to test your scenario, would be with a large cap bank...in-line to a DC load, or resistor network that can handle fast/large transients and log them.  HOWEVER there is a better way to do this.  Just send the output into a capacitive bank...and from there to a variable resistance source....and stick a scopes probes on the last cap in the bank.  That is going to give you a much better representation of the transient, and it's frequency characteristics.  The load is only going to take you so far....

I will set-up a test for you tonight, that shows a method for doing this.....into/through a 5000uF front end....and then leading into an IBV, with another DC-DC POL on it.  I can even do that into a multiphase device if you like.....that is an interesting test.  It can/should be done with something more complex than a simple static load, but I can do it into a variable DCL so you can see what problems and limitations that will result in.  To make it interesting I can use some less than ideal caps, and a less than ideal SMPS as the source....into a VERY sensitive DC-DC solution....that is really the ideal way to do this.  No DCL is going to factor in all the potential turn on issues of a real POL.....if the potential load is a $100k plus PSU, then I wouldn't leave it up to the DC load to stamp some kind of certification on your devices

P.S.  I modified/added to my post above this one, so re-read.